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Module Learning Objectives, Students should be able to:
Interrupts
Exceptions to Program
Execution
Module 8: Part 1 (M8.1)
Describe the nature and mechanisms of
hardware/software synchronization
Explain microcontroller exceptions: types, handlers,
vectors, and priority
ECE 331
Prof. Nihar Mahapatra
(adapted from Prof. A. Mason’s lecture notes; other sources listed at the end)
I/O Synchronization
Embedded systems combine
hardware and software
osoftware executes at MHz (μsec)
speeds
oI/O hardware operates at msec-sec
speeds
ointerfacing software & I/O hardware
requires synchronization
- coordination of timed events
I/O Device Hardware “States”
o idle
- device is disabled or inactive
- no I/O in idle state
o busy
- device is actively performing task
- unable to perform new task yet
- will set a flag when task is complete
o ready
- device is active and awaiting new task M8: Interrupts 2
Concept Terminology
oLatency
- elapsed time between start and end of some operation
- Examples clicking on a web link vs. link opening in browser
oReal-time system
- system with bounded latency system will respond within a given time limit
oBandwidth
- maximum data flow (bytes/sec) possible
oThroughput
- actual rate of data processing or operation completion
oPriority
- order of service when two or more simultaneous service requests are possible
Synchronization Methods
Methods for synchronizing software to I/O
(peripheral) hardware
o NOTE: most peripheral devices generate a “flag” when data is ready or task is done
- flag is a bit within an I/O device control register
- flag can trigger interrupt, if available & enabled methods that consume 100% of processor time
Blind cycle
o wait fixed time for I/O to finish its job o Ex: software delay loop
Busy-wait
o software loop checks flag to know when I/O job is finished o Ex: waiting for SysTick timer flag 3 methods that free processor to perform other tasks
Interrupt (IRQ)
o hardware-generated break in software execution o inputs devices
- request IRQ when new data available interrupt service routine (ISR) stores new input data to memory o output devices
- request IRQ when output is idle “give me more data to send out”
Periodic Polling
o use clock interrupt (like SysTick timer) to periodically check I/O status (via flag) o for tasks that demand interrupt but I/O device does not have a direct interrupt
Direct Memory Access (DMA)
o uses a DMA controller to transfer memory values from input devices or to output devices, without software assistance o DMA synchronization allows high bandwidth and low latency software loop interrupt stores data ISR FIFO= data buffer ? FIFO vs FILO
Output Synchronization
Output synchronization sequence
ooutput device is idle until activated
oonce activated and assigned a task
- output device is busy while performing task
owhen task is complete
- output device enters ready mode waiting for new task
- busy-to-ready transition sets “I’m done” flag
Software duty for synchronization
o1) recognize the ready state (via flag)
o2) assign new task (give new data)
o3) clear flag
- otherwise new flag can not be generated for next task M8: Interrupts 4
Output sequence for
oBlind cycle
oBusy-wait
oInterrupt (using FIFO memory buffer)
Hardware/software interface for
Busy-Wait method
Exception Terminology
otrigger
- asynchronous hardware event that causes an interrupt
othread
- path of action for software execution unique register values and variables for each thread
- ISR is a background thread created by hardware interrupt request killed when ISR is complete
- new thread created by each interrupt
oarm (disarm)
- to enable (disable) an interrupt source, i.e., a trigger
- each interrupt source has an arm bit
oflag
- hardware-generated bit that indicates if an exception has occurred
- readable by software
- typically reset by writing to the flag bit must be cleared by ISR/Handler
oglobal interrupt enable
- system-wide control bit(s) to enable/disable all interrupts from generating flags 7 ARM University Program Copyright © ARM Ltd 2013 8 Microcontroller Exceptions Types of exceptions Hardware interrupts Asynchronous : not related to what code the processor is currently
executing
Examples: interrupt is asserted, character is received on serial port, or ADC
converter finishes conversion
Exceptions, Faults, software interrupts Synchronous : are the result of specific instructions executing Examples: undefined instructions, overflow occurs for a given instruction We can enable and disable ( mask )^ most interrupts as needed
(maskable), others are non-maskable
Interrupt service routine (ISR) Subroutine which processor is^ forced to execute^ to respond to a
specific event
After ISR completes, MCU goes back to previously executing code
Module Learning Objectives, Students should be able to:
Interrupts
ARM Cortex M0 Interrupts
Module 8: Part 2 (M8.2)
Explain interrupts: enabling, processing, and service routines
Describe the CortexM0+ NVIC and exception handling hardware
and mechanisms including operations modes and exception return
codes
Explain the Cortex M0+ hardwired exception processing steps
Describe NVIC configuration, interrupt enabling, and ISR setup
ECE 331
Prof. Nihar Mahapatra
(adapted from Prof. A. Mason’s lecture notes; other sources listed at the end) ARM University Program Copyright © ARM Ltd 2013 10
ARM’s Nested Vectored Interrupt Controller
NVIC manages and prioritizes external interrupts for Cortex-M0+
Interrupts are types of exceptions
Exceptions 16 through 16+N
Modes
Thread Mode: entered on Reset Handler Mode: entered on executing an exception
Privilege level
Stack pointers
Main Stack Pointer, MSP Process Stack Pointer, PSP
Exception states: Inactive, Pending, Active, A&P
ARM Cortex
M0+ Core
Port Module
Next Module NVIC
Another Module
Interrupts and Registers M8: Interrupts
13 SP (R13) refers to PSP or MSP We will use just the MSP
PRIMASK has intr. enable (PM) bit
defaults to enabled
CONTROL defines which stack is
in use
automatically saved
and restored (8 registers)
must be saved by ISR or
will be lost
old R 0 old R 1 old R 2 old R 3 old R 12 old LR old PC old PSR Context Switch Finish instruction a) Push registers b) PC = { 0 x 00000048 } c) Set IPSR = 18 d) Set LR = 0 xFFFFFFF 9 Use MSP as stack pointer Before interrupt RAM Stack
I 0
IPSR 0
MSP
BASEPRI 0
After interrupt Stack
I 0
IPSR 18
MSP
BASEPRI 0
Hardwired Exception Processing
The following actions are hardwired
in the CPU to occur when an
exception occurs
- list is specific to ARM Cortex M0 but similar for most microcontrollers
1. Finish current instruction
2. Push CPU registers onto stack
3. Switch to handler/privileged mode
4. Load PC with address of exception
handler
5. Load LR with EXC_RETURN code
6. Load IPSR with exception number
7. Start executing code in exception
handler
M8: Interrupts 14
3. Switch to handler/privileged
mode
There are two SPs:
oMain (MSP)
oProcess (PSP)
owhich is active depends on operating
mode, CONTROL register bit 1
Handler mode always uses Main SP
We have always used MSP in
Thread Mode
obut useful to know that 2 SPs exist
Thread Mode: MSP or PSP Handler Mode: MSP Reset Starting Exception Processing Exception Processing Completed
Mode, Stack type,
etc. in Keil
Register panel
Mode of Operation
Cortex-M0: two modes of operation
Thread mode
o Used to execute application software
- main program and associated subroutines (main.s)
o foreground operating context
o ISR_NUMBER = 0
Handler mode
o Used to handle exceptions
- routines that service exceptions (startup.s)
o background operating context
o ISR_NUMBER = code for each exception
Changing modes
o processor enters Thread mode from reset
o processor enters Handler mode to start
processing exceptions
o when finished with exception processing,
the processor returns to Thread mode
15
Stack vs. Mode
oMSP
oPSP
- only available in Thread Mode Hardware Hardware needsservice ISRprovides service Busy Done Busy Saves executionstate Restores execution Interrupt state Thread Main Thread time
Hardwired Exception Processing
The following actions are hardwired
in the CPU to occur when an
exception occurs
- list is specific to ARM Cortex M0 but similar for most microcontrollers
1. Finish current instruction
2. Push CPU registers onto stack
3. Switch to handler/privileged mode
4. Load PC with address of exception
handler
5. Load LR with EXC_RETURN code
6. Load IPSR with exception number
7. Start executing code in exception
handler
M8: Interrupts 16
3. Switch to handler/privileged mode
When CPU switches to handler mode
o Mode is changed to handler
Observing these changes in Keil
Mode changed to Handler. Was already using MSP and in Privileged mode
Vectors and Handlers in ROM
Handler = interrupt service routine (ISR)
o written by user
o stored to ROM
relevant exception occurs
Starting location of ISR saved to interrupt vector table
o designated spot in ROM
for each exception source
19
Reset Interrupt Vector^ 0x0000_
Non-Maskable Interrupt Vector
Port A Interrupt Vector
Port D Interrupt Vector
start Reset PC PORTD_IRQHandler PORTD_IRQHandler NMI_IRQHandler NMI_IRQHandler PORTA_IRQHandler 0x0000_ 0x0000_00B 0x0000_00BC PORTA_IRQHandler Reset Interrupt Service Routine i.e. main program
Port D ISR
Port A ISR
Non-maskable
Interrupt
Service Routine
address of Reset handler which runs user code “Main” (0x0000.026D) address of initial SP (0x2000.0240)
Reset
Reset
ooccurs on power up or when reset is
activated (normally by pushing reset button)
oautomatically executes certain
instructions to return to a default state
oSP 32 - bit value from ROM [0]
- stack access is 32-bit word aligned
oPC 32 - bit value from ROM [4]
- ROM [4] is “instruction reset vector” where to look for instr. word after reset
- instructions are half-word aligned M8: Interrupts 20
ARM Core System Handler Vectors
Address Vector IRQ # NVIC IPR Source Source description* 0x0000_0000 0 — — ARM core Initial Stack Pointer 0x0000_0004 1 — — ARM core Reset (Initial Program Counter) 0x0000_0008 2 — — ARM core Non-maskable Interrupt (NMI) 0x0000_000C 3 — — ARM core Hard Fault 0x0000_0010 4 - 10 — — — Reserved 0x0000_002C 11 — — ARM core Supervisor call (SVCall) 0x0000_0030 12 - 13 — — — Reserved 0x0000_0038 14 — — ARM core^ Pendable request (PendableSrvReq) 0x0000_003C 15 — — ARM core System tick timer (SisTick)
Hardwired Exception Processing
The following actions are hardwired
in the CPU to occur when an
exception occurs
- list is specific to ARM Cortex M0 but similar for most microcontrollers
1. Finish current instruction
2. Push CPU registers onto stack
3. Switch to handler/privileged mode
4. Load PC with address of exception
handler
5. Load LR with EXC_RETURN code
6. Load IPSR with exception number
7. Start executing code in exception
handler
Usually 16 cycles from exception
request to execution of first
instruction in handler
21
5. Load LR with EXC_RETURN code
When exception occurs, the
processor could be
orunning in Handler (0) or Thread (1)
mode
ousing MSP (0) or PSP (1) stack pointer
EXC_RETURN value is generated
by CPU to provide information on
how to return from exception
owhich mode
owhich stack pointer
EXC_RETURN is loaded into LR
ooriginal LR (if any) was pushed to
stack in step 2
EXC_RETURN Return Mode Return Stack Description 0xFFFF_FFF1 0 (Handler) 0 (MSP) Return to exception handler 0xFFFF_FFF9 1 (Thread) 0 (MSP) Return to thread with MSP 0xFFFF_FFFD 1 (Thread) 1 (PSP) Return to thread with PSP
Hardwired Exception Processing
The following actions are hardwired
in the CPU to occur when an
exception occurs
- list is specific to ARM Cortex M0 but similar for most microcontrollers
1. Finish current instruction
2. Push CPU registers onto stack
3. Switch to handler/privileged mode
4. Load PC with address of exception
handler
5. Load LR with EXC_RETURN code
6. Load IPSR with exception number
7. Start executing code in exception
handler
M8: Interrupts 22
6. Load IPSR with exception number
When CPU switches to handler mode
o Exception number is loaded into xPSR
- exception number indicates which type of exception has occurred
- exception number = vector = IRQ+0x
Observing these changes in Keil
PORTD_IRQ exception number is 47 = 0x2F
CPU xPSR register
status flags (MSBs) (^) exception number (LSBs) Address Vector IRQ # NVIC IPR Source Source description* 0x0000_00B8 46 30 7 GPIO Pin detect (Port A) 0x0000_00BC 47 31 7 GPIO Pin detect (Port D)
Enabling Interrupts
Global enable of configurable
exceptions
oCPSIE i (assembly instruction)
Enable specific interrupt source in
NVIC
oset NVIC_ISER[x] to 1
- NVIC_ISER address: 0xE000E
- x = NVIC_ISER bit # = IRQ# of interrupt source one control bit for each of the 32 interrupt sources
- e.g., Port A IRQ# = 30
- Port D IRQ# = 31
- see details on next page
Store Exception Handler address to
Vector Table
ocan not store using ASM instructions
ouse DCD directive
25
ARM CPU Special Registers
o PRIMASK : exception mask register
- PM, bit[0]
- PM = 1 global disable of configurable exceptions
- PM = 0 enable configurable exceptions PM = 0 on Reset
- special assembly instructions used to set/clear PRIMASK.PM CPSID i ;sets PRIMASK.PM to 1, disable CPSIE i ;sets PRIMASK.PM to 0, enable
o CONTROL : defines privilege & stack
- nPRIV,bit[0]: defines execution privilege in Thread mode 0 Thread mode has privileged access 1 Thread mode has unprivileged access
- SPSEL,bit[1]: defines current stack 0 Use SP_Main (MSP) as current stack 1 Use SP_Process (PSP) as current stack in Thread mode (no effect in Handler mode) where “ISR_PTD” is a label in ASM code
NVIC Configuration
Interrupt Set-Enable Register
o NVIC_ISER
o Address: 0xE000E
Interrupt Clear Enable Register
o NVIC_ICER
o Address: 0xE000E
write- 1 - to-enable policy (ISER)
write- 1 - to-clear policy (ICER)
both registers read the current
enabled state of corresponding 32
interrupts
M8: Interrupts 26 Extra Info: Not covered in ECE Interrupt Pending Registers o Interrupt has been requested but is not yet serviced; contains status of disabled interrupts o Interrupt Set-Pending Register
- NVIC_ISPR
- Address: 0xE000E o Interrupt Clear-Pending Register
- NVIC_ICPR
- Address: 0xE000E From ARMv6-M Architecture Reference Manual o When an interrupt is disabled, interrupt assertion causes the interrupt to become pending , but the interrupt does not activate. If an interrupt is active when it is disabled, it remains in the active state until this is cleared by a reset or an exception return. Clearing the enable bit prevents any new activation of the associated interrupt. o Software can set or remove the pending state of NVIC interrupts using a complementary pair of registers, the Set-Pending Register and Clear- Pending Register. The registers use a write- one-to-enable and write-one-to-clear policy, and a read of either register returns the current pending state of the corresponding 32 interrupts. Writing 1 to a bit in the Clear- Pending Register has no effect on the execution status of an active interrupt. NVIC Control Bit (= IRQ #) Interrupt Source 12 UART 0 (communication) 17 Timer 0 30 PORTA 31 PORTD
NVIC_ISER
NVIC_ICER
see vector table for full list
Nested Vectored Interrupt Controller (NVIC)
NVIC: block in ARM Cortex core
Role of NVIC:
otake control during Handler Mode
oautomates actions to minimize IRQ
latency (typically 16 cycles)
omanage automated interrupt actions
- storing “processor state” to stack
- restoring processor state at return from ISR
omanage multiple interrupts (dynamic
reprioritization)
- tail-chaining for back-to-back interrupts next IRQ “chained” to the “tail” of last IRQ
- allows higher priority IRQs to preempt others
NVIC Control Registers
o Interrupt Set Enable, NVIC_ISER
- one register with one enable bit for each (of 32 ) peripheral IRQ
oand other registers to set priority
27
Flow path of IRQ sources
NVIC
PRIMASK
“PM” bit [0]
_ISER
_priority
peripheral
interrupt enable
one for each peripheral IRQ source
peripheral device flags
one for each device IRQ generated CPSIE I NVIC, Base: 0xE000.E Enable (_ISER) Offset: 0x 1 32b register 1 bit per source Disable (_ICER) Offset: 0x 1 32b register 1 bit per source Example: PortD_Pin0 IRQ Port D_PCR_BASE: 0x4004.C Pin0 Offset: 0x IRQC [bits 19:16] 0000 = disabled 1000 = interrupt when low
Module Learning Objectives, Students should be able to:
Interrupts
GPIO Interrupts
Module 8: Part 3 (M8.3)
Describe and implement in assembly GPIO interrupt
configuration and ISR functions
Explain and code exception handler exiting
ECE 331
Prof. Nihar Mahapatra
(adapted from Prof. A. Mason’s lecture notes; other sources listed at the end)
Exiting an Exception Handler
Required exception return behavior
o Execute instruction triggering exception
return processing
o Select return stack & restore context from
that stack
o Resume execution of code at restored PC
address
Triggering Return from Exception
o No specific “return from interrupt”
instruction
o Exception return is initiated when:
- processer is in Handler mode AND
- the EXC_RETURN value (0xFXXXXXXX) is loaded into the PC EXC_RETURN defines return Stack and Mode
Thus, Return from Exception is
initiated when the Exception Handler
executes one of the following:
o BX LR
o POP {PC}
- ;if EXC_RETURN was pushed to stack and is now at the top of the stack
During Return from Exception, the
processor automatically
o restores values that it stacked on exception entry o changes to Thread mode
- provided it was in Thread mode prior to entering the exception handler as determined by the EXC_RETURN value o resumes execution of the code that was preempted by the exception handler R R R R R LR PC* xPSR
- previous SP- Address SP+0x SP+0x SP+0x SP+0x0C SP+0x SP+0x SP+0x SP+0x1C Stack Content For reference: CPU register and stack contents when exception handler begins handler start address EXC_RETURN exception number Register PC LR PSR Content 31
Interrupt Conditions and Processing Summary
Three conditions must be true
simultaneously for an interrupt to
occur:
1. Enable: interrupts globally enabled
(I=0 in PRIMASK)
2. Arm: control bit for each possible
source is set
3. Trigger: hardware action sets source-
specific flag
Interrupt serviced once all
conditions become true
o Interrupt remains pending if trigger is
set but any other condition is not true
Need to acknowledge interrupt
o Clear trigger flag or will get endless
interrupts!
M8: Interrupts 32
Interrupt Processing Sequence
automatically performed
1. current instruction is finished
2. push 8 registers (R0-R3, R12, LR,
PC, PSR) on the stack
3. switch to handler/privileged mode
4. set PC to ISR address
- executes ISR on next clock
5. set LR to EXC_RETURN code
- indicates interrupt return
6. set IPSR to interrupt number
7. start executing exception handler
ISR Requirements
o clear flag that requested interrupt
o performs necessary operations
o communicate using global
variables
o resumed main program using
BX LR
- automatically pulls 8 registers from stack
CONTROL & PRIMASK
A mask register, PRIMASK, used to
manage the prioritization scheme for
exceptions and interrupts.
33
A control register, CONTROL that
identifies the current stack.
Special Assembly instructions
References
J.W. Valvano, Introduction to ARM Cortex-M Microcontrollers (Embedded Systems Vol. 1), 4th^ Ed, 2013, ISBN: 978-
J. Yiu, The Definitive Guide to the ARM Cortex-M0 , Elsevier, 2011, ISBN: 978- 0 - 12 - 385477 - 3. J. Yiu, The Definitive Guide to ARM Cortex-M0 and Cortex-M0+ Processors , Elsevier, 2 nd^ Edition, 2015, ISBN: 978 - 0 - 12 - 803277 - 0. 34
