Exception Handling in Microprocessors: Interrupts, Exceptions, and Processing, Slides of Microcomputers

Download Exception Handling in Microprocessors: Interrupts, Exceptions, and Processing and more Slides Microcomputers in PDF only on Docsity!

Exception Handling

Exception Handling

• Interrupts and Exceptions
• An introduction
• Classes and Mechanisms

Exception Handling

• Bridge three components of microprocessor
  • Hardware
  • Software
  • Operating System
• In reality an exception is a call to the OS
• Features common to a subroutine call and may be explicit

Exceptions

• Can be divided into two classes
  • Internal exceptions – those generated by execution of an instruction
  • External exceptions – those caused by actions taken outside the processor chip
• Each class/subclass is handled by its own exception handler – software that is part of OS and responds to the exception

Exceptions

• Alternative is to do useful processing until an event occurs (asynchronously) and then “service” the event
• Interrupt latency – the time from the interrupt occurring (interrupt request) and the processor responding

A typical sequence of actions

• Interrupt (exception) asserted
• Complete current instruction
• Save Program Counter (PC) – this would go on the supervisory stack in the 68000
• Save the state of the processor
  • Stack the registers
• Jump to interrupt (exception) service routine

Nonmaskable interrupt

• Interrupts are “requests”
  • Requests can be serviced, denied or deferred
• Nonmaskabel interrupts (NMI) are those that cannot be denied or deferred
• Examples
  • Low-voltage interrupt detector – response would be to perform orderly shutdown
  • High temperature detector

Prioritized Interrupt

• More than one level of interrupt possible
• Prioritize
  • High level – serviced sooner
    • Example – disk service routine to capture and transfer the data from the disk
  • Medium level – serviced in acceptable time
    • Example – keyboard where data may be held for 200ms
  • Low level – serviced as processing allows
    • Example – continue adding data to printer output buffer

Vectored Interrupts (2)

• IACK – output pin on processor
  • When asserted, requesting device places identification code (number) on bus
  • Processor (in supervisory mode) branches to correct routine to service peripheral
• 68000 has both vectored and non-vectored interrupts

Exceptions

• Roots in the days of mainframes
• “Deviation in normal sequence of actions”
• Interrupts are asynchronous exception
• Hardware error exceptions
  • Trying to read from a memory address not populated
• Software exceptions
  • Error – Ex: Illegal op code
  • Deliberate – Termed a TRAP – can be used to “create new instructions” – Ex: floating point addition

Pseudocode for exception processing

• What happens when an exception occurs

Module Process_exception Begin [Temporary S  1 Register] [SR] {save status register in temporary location}{force supervisor mode} T Get Vector  (^0) Number {turn off trace mode}{calculate exception type number} Address Handler  [M(Address)]VectorNumber x 4 {exception vector is at 4 x vector number}{read table to get address of exception handler} [SSP] [M([SSP])]  [SSP]  [PC] – 4 {predecrement stack pointer{push program counter} } [SSP] [M([SSP])]  [SSP]  [TemporaryRegister] {push status register} – 2 {predecrement stack pointer} [PC] END  Handler {call exception handler}

The handler or Service routine

ProcessException *

BEGIN [SR] (^)  [M([SSP])] {begin the{restore old SR} return from exception sequence-RTE} [SSP] [PC]   [M([SSP])] [SSP] + 2 {restore old PC}

END^ [SSP]^ ^ [SSP] + 4