VHDL Implementation of Multiplexers: 2x1 and 4x1 MUX, Slides of Computer Science

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Multiplexers

Combinational logic circuit

Combinational Circuit Example

8-line 2-to-1 Multiplexer

8-line 2 x 1 MUX

a(7:0)

b(7:0)

y(7:0)

sel

sel y

0 a

1 b

library IEEE; use IEEE.std_logic_1164. all ; entity mux2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) ); end mux2;

Entity

Each entity must

begin with these

library and use

statements

port statement defines

inputs and outputs

library IEEE; use IEEE.std_logic_1164. all ; entity mux2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) ); end mux2;

Entity

Mode: in or out

Data type: STD_LOGIC,

STD_LOGIC_VECTOR(7 downto 0);

Standard Logic

Type std_ulogic is unresolved.

Resolved signals provide a mechanism

for handling the problem of multiple

output signals connected to one signal.

subtype std_logic is resolved

std_ulogic;

architecture mux2_arch of mux2 is begin mux2_1: process (a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if ; end process mux2_1; end mux2_arch;

Architecture

a(7:0) b(7:0) y(7:0) sel 8-line 2 x 1 MUX Note: <= is signal assignment

An 8-line 4 x 1 multiplexer

library IEEE; use IEEE.std_logic_1164. all ; entity mux4 is port ( a: in STD_LOGIC_VECTOR (7 downto 0); b: in STD_LOGIC_VECTOR (7 downto 0); c: in STD_LOGIC_VECTOR (7 downto 0); d: in STD_LOGIC_VECTOR (7 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (7 downto 0) ); end mux4;

Example of case statement

architecture mux4_arch of mux4 is begin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case ; end process ; end mux4_arch; (^) Must include ALL posibilities in case statement Note implies operator => Sel y “00” a “01” b “10” c “11” d

VHDL Process P1: process (<sensitivity list) begin < sequential statements > end process P1 ; Optional process label Within a process: Variables are assigned using := and are updated immediately. Signals are assigned using <= and are updated at the end of the process.