VHDL Design and Implementation of Digital Circuits: Flip-Flops and Multiplexers, Slides of Computer Science

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Flip-flops

Combinational logic circuit

Basic Latch

• Both circuit are the

same

• The only feedback

path is the red line

Reset

Set

Qa

Qb

Reset

Set

Qb

Qa

Basic Latch

• Consider S = 1, R =

– As S=1, NOR1 output must be 0

– As NOR1 ouput = 0 and R =0, NOR2 output must be

NOR

NOR 1

Reset

Set

Qa

Qb

Basic Latch

• Consider S = 0, R =

– As R = 1, NOR2 output must be 0

NOR

NOR 1

Reset

Set

Qa

Qb

Level sensitive and edge sensitive

• For a latch and flip-flop (FF), it can be level

sensitive or edge sensitive

• Level sensitive means the latch / FF will copy input

D to output Q when Clk = 1

• Edge sensitive means that the latch / FF will only

copy input D to output Q when Clk change from 0

-> 1 (positive edge trigger) / 1 -> 0 (negative edge

trigger)

Level sensitive

Clk

D

Q

Representation of Numbers

• Single bit signal

– signal abc : STD_LOGIC; (define signal)

– abc : IN STD_LOGIC; (input port)

• Multibit signal

– signal abc : STD_LOGIC_VECTOR(3 downto 0);

– signal abc : STD_LOGIC_VECTOR(1 to 3);

– abc : IN STD_LOGIC_VECTOR(3 downto 0);

– abc : IN STD_LOGIC_VECTOR(1 to 3);

Assign value to signal

• Vector: signal abc: std_logic_vector(2 downto

– abc <= “101“; (equivalent to the following)

– abc(2) <= ‘1‘;

– abc(1) <= ‘0‘;

– abc(0) <= ‘1‘;

• Single bit: signal abc: std_logic;

– abc <= ‘1‘;

Arithmetic (addition)

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

USE ieee.std_logic_signed.all ;

ENTITY adder16 IS

PORT ( X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;

S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;

END adder16 ;

ARCHITECTURE Behavior OF adder16 IS

BEGIN

S <= X + Y ;

END Behavior ;

Arithmetic (addition)

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN SIGNED(15 DOWNTO 0) ; S : OUT SIGNED(16 DOWNTO 0) ; Cout, Overflow : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : SIGNED(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ; END Behavior ;

Extend to 17 bits, since

signal “Sum” is 17 bit

Carry out is just the

17 th^ bit of “Sum”

Selected signal assignment

• Allows a signal to be assigned one of several

values, based on a selection criterion

• Examples: can be used to implement

multiplexer

• WITH-SELECT statement

4-to-1 Multiplexer

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ;

ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Behavior ;

Selection based on

value of signal “s”. For

example, when “s” is

“00”, value of “w0” will

assigned to “f”

PORT-MAP statement

LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY work ; USE work.mux4to1_package.all ;

ENTITY mux16to1 IS PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux16to1 ;

ARCHITECTURE Structure OF mux16to1 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ; Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

This is an example of building a 16to1 multiplexer

using five 4to1 multiplexer. Port-Map can be

regarded as function call in C language.

PORT-MAP continues

LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE mux4to1_package IS COMPONENT mux4to PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END COMPONENT ; END mux4to1_package ;

To use PORT-MAP to build a 16to

multiplexer using 4to1 multiplexer,

in your working directory, you should

have this file named “mux4to1_package.vhd”