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Cork Institute of Technology
Bachelor of Engineering in Electronic Engineering Stage 3 / Summer 2005 Page 1 of 7
Bachelor of Engineering in Applied Electronics Design - Award
(NFQ Level 7)
Summer 2007
Digital System Design
(Time: 2 Hours)
Answer SIX questions. TWO questions from each section. a=10-18^ , f=10-15^ , p=10-12^ , n=10-9^ , μ=10- m=10 -3^ , k=10^3 , M=10 6
Examiners: Mr. P. Collins Mr. D. Denieffe Dr R. O’Dubhghaill
SECTION A : Questions worth 16 marks each.
For all questions in section A the process is the CN20 process. The process parameters are given in the appendix at the end of this exam paper.
Q1. a) Show that the intrinsic time constant for a minimum sized n-channel device = 38psec and the intrinsic time constant for a minimum sized p-channel device = 114psec. [ 4 marks ] b) Repeat part (a) for a p-channel device whose L is 3 times the minimum value. [ 4 marks ] c) What should L be for an n-channel device to have the same time constant as the p-channel device in part (b)? [ 8 marks ]
Q2. a) A CMOS inverter is made using NMOS and PMOS from the CN20 process. What is the switching point if for the NMOS : L = 15μm , W = 25μm and for the PMOS : L = 20μm , W = 30μm? [ 4 marks ] b) Assuming that the NMOS device remains unchanged , modify the PMOS device so that the inverter switching point is 2.5V. For the purposes of the calculations you can assume that the threshold voltages of the 2 devices are close enough to be considered equal. [ 8 marks ] c) Calculate the intrinsic propagation delays , tPLH and t (^) PHL , for the inverter in part (a). [ 4 marks ]
Q3.
a) Draw the circuit diagram of a 2-input NOR gate. [ 4 marks ]
b) Calculate the switching point of a 2-input NAND gate if the NMOS devices have L=10μm , W = 20μm and if the PMOS devices have L=40μm , W=50μm. [ 4 marks ] c) Estimate the intrinsic propagation delay of the 2-input NAND gate. Assume that the inputs are tied together and assume that Cload = 0. [ 8 marks ]
SECTION B : Questions worth 16 marks each.
Q4. a) What do the following terms stand for : PLD , SPLD , CPLD , PAL , GAL , PLA , PROM , FPGA , HDL , ISP? [ 5 marks ]
b) How does a CPLD differ from an SPLD? [ 1 mark ] c) Explain the difference between a PLA , a PAL and a GAL. [ 6 marks ]
d) Give 2 advantages of PLDs over fixed function logic devices. [ 2 marks ]
e) What is an antifuse on a programmable device? [ 2 marks ]
Q5.
a) Explain the term ‘ logic array block’ and ‘ programmable interconnect array’ for a CPLD. [ 8 marks ] b) A logic array block is divided into macrocells. Describe the contents of a typical macrocell. [ 8 marks ]
Q6. a) An FPGA does not use the AND/OR logic structure associated with a CPLD. What does it use instead? Explain how the replacement implements logic functions. Use the example of a circuit that compares two 2-bit numbers for equality to clearly explain the operation. The numbers are A 1 A 0 and B 1 B 0. The output , E , is 1 if A 1 A 0 =B 1 B 0 and is 0 otherwise ( e.g. if A 1 A 0 =’01’ and if B 1 B 0 =’01’ then E=’1’). (^) [ 12 marks ]
b) Typically what method is used to control which interconnections are made on an FPGA and why does this method mean that FPGAs lose their configuration when power is removed. [ 4 marks ]
Q9.
A BCD/Decimal decoder has one 4-bit input port and 10 output ports. The value of the input port is used to set one of the output ports high. The truth table is :
INPUTS OUTPUTS
A3 A2 A1 A0 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP8 OP
Implement the decoder in VHDL in 2 different ways. You can use any 2 different techniques of your choice for the architecture. The bit_vector data type should be used.
[ 18 marks ]
APPENDIX.
- CN20 process parameters for NMOS and PMOS.
Process CN20 NMOS CN20 PMOS Vdd ( Vss = 0 ) 5V 5V Lmin 2 μm 2 μm Wmin 3μm 3 μm V (^) THN or VTHP 0.83V 0.91V KP ( μ A/V^2 ) 50 17 C’ox 800 aF/μm^2 800 aF/μm^2 Rn or Rp 12kΩL/W^ 36kΩL/W τ n or τ p 38ps 114ps
- VHDL templates ( N.B. Not all are necessary for this exam ).
_An underscore in front of a word means that it is replaced by the appropriate VHDL construct in practice. ( e.g. _signal_name is replaced by a valid VHDL signal name , statement is replace by a valid VHDL statement ). ----- Library declaration. LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; ----- Architecture declaration. _ARCHITECTURE a OF __entity_name IS ----- SIGNAL declaration SIGNAL __signal_name : STD_LOGIC; SIGNAL _signal_name : STD_LOGIC; ----- COMPONENT declaration ( if needed ). BEGIN END a; ----- Case statement. _CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; _statement;
___process_label: PROCESS (__signal_name, __signal_name, _signal_name) BEGIN
_END PROCESS _process_label;
----- Selected signal assignment. ( concurrent case statement )
___label: WITH __expression SELECT __signal <= __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN _constant_value;
------ Signal declaration.
_SIGNAL __signal_name : _type_name;
----- Signal assignment.
___signal_name <= _expression;
