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CORK INSTITUTE OF TECHNOLOGY
INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ
Module Title: Electronics
Module Code: ELXE E
School: School of Electrical & Electronic Engineering
Programme Title: Bachelor of Engineering (Honours) in Electronic Engineering – Award
Programme Code: EELXE_8_Y
External Examiner(s): Prof. G. Hurley Dr. S. Foley
Internal Examiner(s): Dr. J. Barrett Mr. P. Collins
Instructions: There are two Sections (A and B)
Answer any five questions. Please use separate answer books for each section. Each question carries equal marks (20)
Maximum available mark is 100.
Duration: 3 HOURS
Sitting: Winter 2007
Requirements for this examination: N/A
Note to Candidates: Please check the Programme Title and the Module Title to ensure that you have received the correct examination paper. If in doubt please contact an Invigilator.
Section A - IC Design
Q a) Explain the following terms associated with Sample and Hold circuits : Pedestal Error, Droop Rate, Isolation, Aperture Jitter. [ 8 marks ]
b) For a Sample and Hold circuit made using a MOS switch, a capacitor and an amplifier, derive an expression for the pedestal error in terms of the relevant switch parameters, the hold capacitor, the supply voltage and the input voltage to the sample and hold. [ 6 marks ]
c) Draw a schematic for a high input impedance Sample and Hold circuit which produces a pedestal error which is not significantly affected by the input voltage level. Explain how the circuit works in both sample mode and hold mode. Discuss the effect of the offset voltages of any gain or buffer elements. [ 6 marks ]
Q. a) A signal of interest being sampled by an ADC has a bandwidth of fO but is sampled at a frequency f (^) S ( where f (^) S > 2f (^) O) by the ADC. The ADC is followed by a brickwall digital low pass filter with passband f (^) O. If OSR = f (^) S/2f (^) O show that the SNR of the system is : SNR = 6.02N + 1.76 + 10log 10 (OSR). [ 5 marks ]
b) Explain how a 1 st^ order delta-sigma modulator can be used to shape the quantization noise of a quantizer. Make reference to the noise transfer function and the signal transfer function in your explanation. [ 5 marks ]
c) The magnitude of the Noise Transfer Function of a 1 st^ order delta-sigma modulator
is (^)
f S
f NTF Sin
- Show that the quantization noise power is :
3
36 OSR
PE
f (^) S is the sampling frequency of the ADC. f (^) O is the frequency range of interest on the input. OSR = f (^) S /2f (^) O. ∆ is the LSB size.
The spectral density of the quantization noise is S
E f
S
[ 6 marks ]
d) Using the equation for P (^) E from part (c), show that the maximum SNR of a 1 st^ order delta-sigma N-bit ADC = 6.02N + 1.76 - 5.17 + 30*log 10 (OSR) for a sine wave input signal. [ 4 marks ]
Q
a) A BCD/Decimal decoder is a circuit that has one 4-bit input port and 10 output ports. The value of the input port is used to set one of the output ports high. The truth table is shown in Fig Q4a. Write VHDL code for a behavioral model of the decoder. You should make use of a Case statement and logic vectors in your answer. [ 8 marks ]
INPUTS OUTPUTS A3 A2 A1 A0 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP8 OP 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1
Fig Q4a.
b) A logic block has the following inputs : a clock signal, serial data line, polarity control line. It has one output, Q. The block is to look for an occurrence of the sequence ‘101’ in the input serial stream if the polarity control line is high, and for an occurrence of the sequence ‘010’ if the polarity control line is low. After an occurrence of the correct input pattern, the output is to go high for 3 clock cycles. The serial data input can be ignored during these 3 cycles. The block should then start monitoring the input again. Write VHDL code that uses a state machine to implement the logic block. [ 12 marks ]
PART B: RF ELECTRONICS
Q5 Impedance matching
(a) In what circumstances is stub matching preferable to lumped element LC matching and why? (4 marks) (b) A 75Ω source is to be used to feed a load impedance with an input impedance of (150-j85) Ω. Use the Smith Chart provided to find the distance from the load and length (in wavelengths) of a shunt shorted transmission line stub that will match the source and load at 903MHz. (6 marks) (c) Use the Smith Chart to design a two-element lumped LC matching network, blocking DC, to match the same source and load as in part (b) above. (6 marks) (d) What is a “quarter wave transformer” and how is it used? (4 marks)
Q6 S-parameters and small signal amplifiers
(a) In small signal amplifier design, to what common circuit measurements do the four s-parameters relate? (2 marks) (b) Given:
where
• T k = path gain of the k th^ forward path
• ∆ = 1 – Σ(all individual loop gains) + Σ(loop gain products of all possible
combinations of 2 non-touching loops ) – Σ(loop gain products of all possible combinations of 3 non-touching loops) + .....
• ∆k = The value of ∆ for loops not touching the kth^ forward path
Show, for the two port network signal flow graph given in Figure Q6, that for a matched load and an arbitrary source reflection coefficient: (6 marks)
Figure Q
k
Tk k
T
11 S
12 21 S 22 2
2
s
s s
s
a
b
out
APPENDIX A: VHDL Language Reference
_An underscore in front of a word means that it is replaced by the appropriate VHDL construct in practice. ( e.g. _signal_name is replaced by a valid VHDL signal name , statement is replace by a valid VHDL statement ).
----- Library declaration.
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL;
----- Architecture declaration.
_ARCHITECTURE a OF _entity_name IS
_----- SIGNAL declaration SIGNAL __signal_name : STD_LOGIC; SIGNAL _signal_name : STD_LOGIC;
----- COMPONENT declaration ( if needed ).
BEGIN
END a;
----- Case statement.
_CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; _statement; END CASE;
----- Component declaration.
_COMPONENT __component_name PORT( __input_name, __input_name : IN STD_LOGIC; __bidir_name, __bidir_name : INOUT STD_LOGIC; __output_name, _output_name : OUT STD_LOGIC); END COMPONENT;
----- Component instantiation.
___instance_name: __component_name PORT MAP (__component_port => __connect_port, __component_port => _connect_port);
----- Concurrent signal assignment statement.
___signal <= _expression;
------ Conditional signal assignment. ( concurrent if statement ).
___label: __signal <= __expression WHEN __boolean_expression ELSE __expression WHEN __boolean_expression ELSE _expression;
----- Constant declaration.
_CONSTANT __constant_name : __type_name := _constant_value;
----- Entity declaration
_ENTITY __entity_name IS PORT( __input_name, __input_name : IN STD_LOGIC; __input_vector_name : IN STD_LOGIC_VECTOR(__high downto _low); __bidir_name, __bidir_name : INOUT STD_LOGIC; __output_name, __output_name : OUT STD_LOGIC); END _entity_name;
----- For statement.
___loop_label: FOR __index_variable IN __range LOOP __statement; __statement; END LOOP _loop_label;
----- If statement.
_IF __expression THEN __statement; __statement; ELSIF __expression THEN __statement; __statement; ELSE __statement; _statement; END IF;
_state <= __state_name; END IF; WHEN __state_name => IF __condition THEN state <= _state_name; END IF; END CASE; END IF; END PROCESS;
_WITH state SELECT __output_name <=__output_value WHEN __state_name, __output_value WHEN __state_name, __output_value WHEN _state_name; END a;
