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Random access memory
• Sequential circuits all depend upon the presence of memory.
– A flip-flop can store one bit of information.
– A register can store a single “word,” typically 32-64 bits.
• Random access memory, or RAM, allows us to store even larger amounts
of data. Today we’ll see:
– The basic interface to memory.
– How you can implement static RAM chips hierarchically.
• This is the last piece we need to put together a computer!
Introduction to RAM
• Random-access memory, or RAM, provides large quantities of temporary
storage in a computer system.
• Remember the basic capabilities of a memory:
– It should be able to store a value.
– You should be able to read the value that was saved.
– You should be able to change the stored value.
• A RAM is similar, except that it can store many values.
– An address will specify which memory value we’re interested in.
– Each value can be a multiple-bit word (e.g., 32 bits).
• We’ll refine the memory properties as follows:
A RAM should be able to:
- Store many words, one per address
- Read the word that was saved at a particular address
- Change the word that’s saved at a particular address
Block diagram of RAM
• This block diagram introduces the main interface to RAM.
– A Chip Select, CS, enables or disables the RAM.
– ADRS specifies the address or location to read from or write to.
– WR selects between reading from or writing to the memory.
4 To read from memory, WR should be set to 0. OUT will be the n-bit value stored at ADRS. 4 To write to memory, we set WR = 1. DATA is the n-bit value to save in memory.
• This interface makes it easy to combine RAMs together, as we’ll see.
2 k^ x n memory
ADRS OUT DATA CS WR
k n
n
CS WR Memory operation 0 x None 1 0 Read selected word 1 1 Write selected word
Memory sizes
• We refer to this as a 2k^ x n memory.
– There are k address lines, which can specify one of 2k^ addresses.
– Each address contains an n-bit word.
• For example, a 2^24 x 16 RAM contains 2^24 = 16M words, each 16 bits long.
– The RAM would need 24 address lines.
– The total storage capacity is 2^24 x 16 = 2^28 bits.
2 k^ x n memory
ADRS OUT DATA CS WR
k n
n
Typical memory sizes
• Some typical memory capacities:
– PCs usually come with 128-256MB RAM.
– PDAs have 8-64MB of memory.
– Digital cameras and MP3 players can have
32MB or more of storage.
• Many operating systems implement virtual
memory, which makes the memory seem larger than it really is.
– Most systems allow up to 32-bit addresses.
This works out to 2^32 , or about four billion, different possible addresses.
– With a data size of one byte, the result is
apparently a 4GB memory!
– The operating system uses hard disk space
as a substitute for “real” memory.
Address Data 00000000 00000001 00000002
..........
FFFFFFFD FFFFFFFE FFFFFFFF
Reading RAM
• To read from this RAM, the controlling circuit must:
– Enable the chip by ensuring CS = 1.
– Select the read operation, by setting WR = 0.
– Send the desired address to the ADRS input.
– The contents of that address appear on OUT after a little while.
• Notice that the DATA input is unused for read operations.
2 k^ x n memory
ADRS OUT DATA CS WR
k n
n
Static memory
• How can you implement the memory chip?
• There are many different kinds of RAM.
– We’ll start off discussing static memory, which is most commonly
used in caches and video cards.
– Later we mention a little about dynamic memory, which forms the
bulk of a computer’s main memory.
• Static memory is modeled using one latch for each bit of storage.
• Why use latches instead of flip flops?
– A latch can be made with only two NAND or two NOR gates, but a
flip-flop requires at least twice that much hardware.
– In general, smaller is faster, cheaper and requires less power.
– The tradeoff is that getting the timing exactly right is a pain.
Starting with latches
• To start, we can use one latch to store each bit. A one-bit RAM cell is
shown here.
• Since this is just a one-bit memory, an ADRS input is not needed.
• Writing to the RAM cell:
– When CS = 1 and WR = 1, the latch control input will be 1.
– The DATA input is thus saved in the D latch.
• Reading from the RAM cell and maintaining the current contents:
– When CS = 0 or when WR = 0, the latch control input is also 0, so
the latch just maintains its present state.
– The current latch contents will appear on OUT.
• In normal practice, it’s bad to connect outputs together. If the outputs
have different values, then a conflict arises.
• The standard way to “combine” outputs is to use OR gates or muxes.
• This can get expensive, with many wires and gates with large fan-ins.
Connecting outputs together
The “C” in LogicWorks means “conflict.”
Those funny triangles
• The triangle represents a three-state buffer.
• Unlike regular logic gates, the output can be one of three different
possibilities, as shown in the table.
• “Disconnected” means no output appears at all, in which case it’s safe to
connect OUT to another output signal.
• The disconnected value is also sometimes called high impedance or Hi-Z.
EN IN OUT 0 x Disconnected 1 0 0 1 1 1
Bigger and better
• Here is the 4 x 1 RAM
once again.
• How can we make a
“wider” memory with more bits per word, like maybe a 4 x 4 RAM?
• Duplicate the stuff in
the blue box!
A 4 x 4 RAM
• DATA and OUT are now each four bits long, so you can read and write
four-bit words.
8
8
16
Making a larger memory
• We can put four 64K x 8 chips
together to make a 256K x 8 memory.
• For 256K words, we need 18
address lines.
– The two most significant
address lines go to the decoder, which selects one of the four 64K x 8 RAM chips.
– The other 16 address lines are
shared by the 64K x 8 chips.
• The 64K x 8 chips also share WR
and DATA inputs.
• This assumes the 64K x 8 chips
have three-state outputs.
Analyzing the 256K x 8 RAM
• There are 256K words of memory,
spread out among the four smaller 64K x 8 RAM chips.
• When the two most significant
bits of the address are 00, the bottom RAM chip is selected. It holds data for the first 64K addresses.
• The next chip up is enabled when
the address starts with 01. It holds data for the second 64K addresses.
• The third chip up holds data for
the next 64K addresses.
• The final chip contains the data of
the final 64K addresses.
8
8
16
