Docsity
Log inSign up
Docsity
Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity

Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan

Guidelines and tips
Guidelines and tips
Sell on Docsity
Sell on Docsity
Docsity AI
Docsity AI
Log inSign up

Prepare for your exams

Study with the several resources on Docsity

Find documents

Prepare for your exams with the study notes shared by other students like you on Docsity

Search for your university

Find the specific documents for your university's exams

Docsity AINEW

Summarize your documents, ask them questions, convert them into quizzes and concept maps

Explore questions

Clear up your doubts by reading the answers to questions asked by your fellow students

Earn points to download

Earn points by helping other students or get them with a premium plan

Share documents
download point icon20 Points

For each uploaded document

Answer questions
download point icon5 Points

For each given answer (max 1 per day)

All the ways to get free points
Get points immediately

Choose a premium plan with all the points you need

Study Opportunities

Choose your next study program

Get in touch with the best universities in the world. Search through thousands of universities and official partners

Community

Ask the community

Ask the community for help and clear up your study doubts

Free resources

Our save-the-student-ebooks!

Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors

Understanding Objects and Signals in VHDL: Signals vs Variables vs Constants, Slides of Computer Science

Amity University - BiharComputer Science

An overview of objects in vhdl, focusing on signals, variables, and constants. Signals are used for communication between entities, variables for local storage in process statements and subprograms, and constants for assigning specific values. Learn about their differences, declarations, and usage.

Typology: Slides

2012/2013

Uploaded on 03/23/2013

dhruv
dhruv 🇮🇳

4.3

(12)

194 documents

1 / 15

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
1
Data Object
Object Types
A VHDL object consists of one of the
following:
–Signal, Which represents interconnection wires
that connect component instantiation ports
together.
–Variable, Which is used for local storage of
temporary data, visible only inside a process.
–Constant, which names specific values.
Docsity.com
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff

Partial preview of the text

Download Understanding Objects and Signals in VHDL: Signals vs Variables vs Constants and more Slides Computer Science in PDF only on Docsity!

1

Data Object

Object Types

A VHDL object consists of one of the following:

  • Signal, Which represents interconnection wires that connect component instantiation ports together.
  • Variable, Which is used for local storage of temporary data, visible only inside a process.
  • Constant, which names specific values.

2

Objects

  • Objects are used to represent & store the data in the system being described in VHDL.
  • Object contains a value of a specific type.
  • The name given to object is called identifier.
  • Each object has a type & class.
    • Class indicates how the object is used in the model & what can be done with the object.
    • Type indicates what type of data the object contains.

4

  • Signal objects can be regarded as wires in a circuit while variable and constant objects are analogous to their counterparts in a high-level programming language like C or Pascal.
  • Signal objects are typically used to model wires and flip-flops while variable and constant objects are typically used to model the behavior of the circuit.

5

Signal

  • Signal objects are used to connect entities together to form models.
  • Signals are the means for communication of dynamic data between entities.
  • A signal declaration looks like this: Signal Signal_name : Signal_type [:= initial_value]

The Keyword SIGNAL is followed by one or more signal names.

7

  • Signals in package declaration are also referred to as global signals because they can be shared among entities.
  • Each signal has a history of values I.e. holds a list of values which include current value of signal & set of possible future values that are to appear on the signal.
  • Computed value is assigned to signal after delay called ‘delta delay’.

8

Signal Declarations

Here are some examples of signal declarations.

signal CLOCK: BIT;

signal DATA_BUS: BIT_VECTOR(0 to 7);

signal GATE_DELAY: TIME := 10 ns;

10

  • The keyword VARIABLE is followed by one or more variable names.
  • Each name creates a new variable.
  • The construct variable_type defines the data type of the variable, and an optional initial value can be specified.
  • Variable can be declared in the process declaration and subprogram declaration sections only.

11

  • Variable are inherently more efficient because assignments happen immediately, while signals must be scheduled to occur.
  • Variables take less memory, while signals need more information to allow for scheduling and signal attributes.
  • Using a Signal would have required a WAIT statement to synchronize the signal assignment to the same execution iteration as the usage.

13

Signal vs Variables

  • A Signal has three properties attached to it: type, value and time. while a variable has only two properties attached to it type and value.
  • Use signals as channels of communication between concurrent statement. In non-synthesizeable models, avoid using signals to describe storage elements. Use variable instead.
  • Signals occupy about two orders of magnitude more storage than variable during simulation. Signals also cost a performance penalty due to the simulation overhead necessary to maintain the data structures representing signals.

14

Constants

  • Constant objects are names assigned to specific values of a type.
  • Constants give the designer the ability to have a better-documented model, and a model that is easy to update.
  • Constant declaration :

Constant constant_name : type_name [:value];