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Main points of this exam paper are: Octal Notation, Numbers and Arithmetic, Decimal Notation, Binary Values, Computer Engineering, Hexidecimal Notation, Octal Notation, Following Hexadecimal, AdditionSubtraction, Complement Representation
Typology: Exams
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4 problems, 6 pages Exam Two 21 March 2001
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck!
Your Name ( please print ) ________________________________________________
1 2 3 4 total
4 problems, 6 pages Exam Two 21 March 2001
Problem 1 ( parts, 35 points) Numbers and Arithmetic
Part A (4 points) Convert these binary values (and powers of two) into decimal notation:
binary notation decimal notation
218
Part B (2 points) Convert this decimal value into hexidecimal notation:
decimal notation hexadecimal notation 91
Part C (4 points) Convert the following hexadecimal values into octal notation:
hexadecimal notation octal notation 0x9C
0x5E.
Part D (9 points) For each problem below, (a) compute the addition or subtraction using the rules of arithmetic (note that the third problem is a subtraction) , (b) indicate whether an error occurs assuming all numbers are expressed using a four bit two’s complement representation, and (c) indicate whether an error occurs assuming all numbers are expressed using a four bit unsigned representation.
result signed error? unsigned error?
4 problems, 6 pages Exam Two 21 March 2001
Problem 2 (3 parts, 30 points) Counter Design
Part A (10 points) Design a toggle cell using transparent latches, 2-input XOR gates, and 2-input basic gates (AND, OR, NAND, NOR, and NOT). Use icons for the latches. Your toggle cell should have an
active high toggle enable input TE , and an active low clear input Clear , two-phase non-overlapping
clock inputs Φ 1 and Φ 2 , and an output Out. The Clear signal has precedence over TE. Label all signals. You should have a single output OUT.
Part B (10 points) Now use several of your toggle cells (in icon form) to build a divide by eight counter. This design should include a count enable CE and an active high clear CLR. You do not need to draw in the clock signals. Assume all toggle cells are connected to the two-phase clock. Use any basic gates (AND, OR, NAND, NOR, and NOT) you require. Label all signals.
Part C (10 points) Now use copies of your toggle cells (in icon form) to build a divide by three counter. This design should include an active high external count enable CE and an active high external clear CLR. Your design should clear if (A) the external clear CLR is high, or (B) the maximum output count is reached and the count enable is high. You do not need to draw in the clock signals.
4 problems, 6 pages Exam Two 21 March 2001
Problem 3 (3 parts, 20 points) State Machines
Out In register
A
Out In register
S S
O
O
Part A (8 points) Complete the state table for the state machine shown above.
A S 1 S 0 O 1 O 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Part B (10 points) Complete the state diagram below for this device by adding all required transition arcs with input annotations. Output annotations are not required since they correspond to the new state.
state 00
state 01
state 10
Part C (2 points) In 6 words or less, describe the function this device implements.
