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Main points of this exam paper are: Positive Value, Representations and Arithmetic, Computer Engineering, Decimal Notation, Octal Notation, Binary Notation, Building Blocks, Badly Stated, Arithmetic, Complement Fixed-Point
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4 problems, 5 pages Exam Two 25 October 2006
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck!
Your Name ( please print ) ________________________________________________
1 2 3 4 total
4 problems, 5 pages Exam Two 25 October 2006
Problem 1 (3 parts, 28 points) Representations and Arithmetic
Part A (10 points) Convert the following notations:
binary notation decimal notation 11011
238 hexadecimal notation octal notation
DA.FA
Part B (10 points) For the 24 bit representations below, determine the most negative value, most positive value, and step size (difference between sequential values). All answers should be expressed in decimal notation. Fractions (e.g., 3/16ths) may be used. All signed representations are two’s complement.
representation most negative value most positive value step size
signed integer (24 bits). (0 bits) unsigned fixed-point (12 bits). (12 bits) unsigned fixed-point (18 bits). (6 bits) signed fixed-point (18 bits). (6 bits)
Part C (8 points) Complete the statements and answer the questions.
“A fixed-point representation has a constant __________________________________
where a floating-point presentation has a constant _____________________________.”
A 32 bit single precision floating point representation has a 23 bit mantissa field, an eight bit exponent field, and one sign bit.
4 problems, 5 pages Exam Two 25 October 2006
Problem 3 (3 parts, 24 points) Badly Stated
Part A (8 points) Implement a transparent latch using only the 2 to 1 mux, NAND gate and NOR gate below. Label the inputs In and En , and output Out.
Part B (8 points) Implement a register with write enable using only transparent latches and NAND gates. Use an icon for the transparent latches. Label the inputs In , WE, Φ 1 , Φ 2 and the output Out.
Part C (8 points) Assume the following signals are applied to your register. Draw the output signal Out. Draw a vertical line where In is sampled. Assume Out starts at zero.
4 problems, 5 pages Exam Two 25 October 2006
Problem 4 (2 parts, 22 points) Arithmetic
Part A (16 points) For each problem below, compute the operations using the rules of arithmetic, and indicate whether an overflow occurs assuming all numbers are expressed using a four bit unsigned fixed-point and four bit two’s complement fixed-point representations.
result
unsigned error? signed error?
Part B (6 points) Consider an arithmetic unit that either adds or subtracts two 32-bit values (X
and Y) based on a control signal ADD / SUB. The result is Z. Define the behavior for a 32 bit two’s complement overflow detection unit. Assume the inputs are X 31 , Y 31 , Z 31 , and
ADD / SUB. The output Error is 1 for overflow.
X 31 Y 31 Z 31 Error X 31 Y 31 Z 31 Error
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1
