CS551- Operating system design and Implementation
Solutions for Homework2
Sol 2.1:
It is central because there is so much parallel or pseudoparallel activity—multiple
user processes and I/O devices running at once. The multiprogrammingmodel allows this
activity to be described and modeled better.
Sol 2.4:
Generally, high level languages do not allow one the kind of access to CPU
hardware that is required. For instance, an interrupt handler may be required to enable
and disable the interrupt servicing a particular device, or to manipulate data within a
process’ stack area. Also, interrupt service routines must execute as rapidly
as possible.
Sol 2.6:
It would be difficult, if not impossible, to keep the file system
consistent using the model in part (a) of the figure. Suppose that a client
process sends a request to server process 1 to update a file. This process
updates the cache entry in its memory. Shortly thereafter, another client
process sends a request to server 2 to read that file. Unfortunately, if the file
is also cached there, server 2, in its innocence, will return obsolete data. If
the first process writes the file through to the disk after caching it, and server
2 checks the disk on every read to see if its cached copy is up-to-date, the
system can be made to work, but it is precisely all these disk accesses that
the caching system is trying to avoid.
Sol 2.13:
Yes, it still works, but it still is busy waiting, of course.
Sol 2.17:
With round robin scheduling it works. Sooner or later L will run, and eventually it
will leave its critical region. The point is, with priority scheduling, L never gets to run at
all; with round robin, it gets a normal time slice periodically, so it has the chance to leave
its critical region.
Sol 2.20:
It does not lead to race conditions (nothing is ever lost), but it is effectively busy
waiting.
Sol 2.26:
The CPU efficiency is the useful CPU time divided by the total CPU time. When
Q ≥T, the basic cycle is for the process to run for T and undergo a process switch for S.
Thus (a) and (b) have an efficiency of T /(S + T). When the quantum is shorter than T,
each run of T will require T /Q process switches, wasting a time ST /Q. The efficiency
here is then T/(T+ST/Q) which reduces to Q/(Q + S), which is the answer to (c). For (d),
