Paged Segmentation in Operating Systems: A Comparison of MULTICS and Intel 80386, Lecture notes of Operating Systems

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Operating

Systems

Paged Segmentation

Syed Mansoor Sarwar

Agenda for Today

MULTICS under GE 345

Memory Management in Intel

Paged Segmentation

MULTICS Example

15 3921

3 849

3921

12 12 849

13137

5096

Intel 80386 Example

4-byte page table entry

32-entry TLB, covering 32*4K

(128 KB) memory … TLB

Reach

Intel 80386 Example

13-bit Segment #

16-bit

Selector

g p

32-bit Offset

s

2-bit field for

specifying the

privilege level

1-bit field to

specify GDT or

LDT

Intel 80386 Example

Protected Mode

48 bytes virtual address space

32 bytes linear address space

Max segment size = 4 GB

Max segments / process = 16K

Six CPU registers allow access

to six segments at a time

Intel 80386 Example

Protected Mode

Selector is used to index a

segment descriptor table to

obtain an 8-byte segment

descriptor entry. Base address

and offset are added to get a

32-bit linear address, which is

partitioned into p1, p2, and d for

supporting 2-level paging.