W4118 Operating Systems
Instructor: Junfeng Yang
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Operating Systems: Paging and Page Translation, Essays (high school) of Computer science
A set of lecture notes for the w4118 operating systems course, focusing on paging and page translation in operating systems. It covers topics such as page table structure, page protection, page sharing, and page table management strategies. It also includes examples and exercises to illustrate these concepts.
Typology: Essays (high school)
2014/2015
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W4118 Operating Systems^ Instructor: Junfeng Yang
Outline
^ Paging^ ^ Overview^ ^ Page translation^ ^ Page allocation^ ^ Page protection^ ^ Translation Look-aside Buffers (TLB)^ ^ Page sharing^ ^ Page table structure^ ^ Combining paging with segmentation
Page translation
^ Address bits =
page number
+^ page offset ^ Translate^ virtual page number (vpn)
to^ physical page number (ppn)
using^ page table pa = page_table[va/pg_sz] + va%pg_sz CPU^ vpn
off^ ppn
off ppnvpn Page table
ppn^ Memory
Page translation example Page 0 Page 1 Page 2 Page 3
Page 0 Page 2 01 14 23 Page 3^
Page 2^ Page 1 Page 3 Page table
PhysicalMemory VirtualMemory
23 37
Page protection
^ Implemented by associating
protection bits with each virtual page in page table Protection bits^ ^ valid bit: map to a valid physical page?^ read/write/execute bits
: can read/write/execute? ^ read/write/execute bits
: can read/write/execute? ^ Checked by MMU on each memory access
Page protection example Page 0 Page 1 Page 3
Page 0 vrwe 011100141110230000 Page 3
Page 1 Page 3 Page table
PhysicalMemory VirtualMemory
23 37 1111
Implementation of page table Page table is stored in memory Page table base register (PTBR)
points to the base of page table OS stores the value of this register in
process control block (PCB) OS switches PTBR on each context switch OS switches PTBR on each context switch Problem: each data/instruction access requirestwo memory accesses Extra memory access for page table
Avoiding extra memory access Fast-lookup hardware cache called associative memory
or^ translation look-
aside buffers (TLBs) Fast^ parallel search (CPU speed) Fast^ parallel search (CPU speed) Small
VPN^ PPN
TLB Miss
^ Can be handled in hardware and software ^ Hardware (CISC: x86)^ ^ Pros: hardware doesn’t have to trust OS!^ ^ Cons: complexity ^ Software (RISC: MIPS, SPARC)^ ^ Pros: flexibility^ ^ Cons: code may have bug^ ^ Question: what can’t a TLB miss handler do?
TLB and context switches What happens to TLB on context switches? Option 1: flush entire TLB x86 Option 2: attach process ID to
TLB^ entries ^ Option 2: attach process ID to
TLB^ entries ^ ASID: Address Space Identifier ^ MIPS, SPARC
Motivation for page sharing Efficient communication.
Processes communicate by write to shared pages Memory efficiency.
One copy of read-only code/data shared among processescode/data shared among processes^ ^ Example 1: multiple instances of the shell program^ ^ Example 2: parent and forked child share AS