Intel x86 Paging Scheme: Understanding Virtual Memory and Page Translation, Slides of Computer Applications

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IA32 Paging Scheme

Introduction to the Intel x86’s

support for “virtual” memory

What is ‘paging’?

• It’s a scheme for dynamically remapping

addresses for fixed-size memory-blocks

Physical address-space Virtual address-space

Why use ‘paging’?

• Use of ‘paging’ allows ‘relocations’ to be

done just once (by the linker), and every

program can ‘reuse’ the same addresses

Task #

Task #

Task #

physical memory

Several ‘paging’ schemes

• Intel’s design for ‘paging’ has continued to

evolve since its introduction in 80386 CPU

• New processors support the initial design,

as well as several optional extensions

• We shall describe the initial design which

is simplest and remains as the ‘default’

• It is based on subdividing the entire 4GB

virtual address-space into 4KB blocks

Control Register CR

• Register CR3 is used by the CPU to find

the tables in memory which will define the

address-translation that it should employ

• This table is called the ‘Page Directory’

and its address must be ‘page-aligned’

Physical Address of the Page-Directory

Page-Directory

• The Page-Directory occupies one frame,

so it has room for 1024 4-byte entries

• Each page-directory entry may contain a

pointer to a further data-structure, called a

Page-Table (also page-aligned 4KB size)

• Each Page-Table occupies one frame and

has enough room for 1024 4-byte entries

• Page-Table entries may contain pointers

Address-translation

• The CPU examines any virtual address it

encounters, subdividing it into three fields

offset into page-frame

index into page-directory

index into page-table

10-bits 10-bits 12-bits This field selects one of the 1024 array-entries in the Page-Directory

This field selects one of the 1024 array-entries in that Page-Table

This field provides the offset to one of the 4096 bytes in that Page-Frame

Page-Level ‘protection’

• Each entry in a Page-Table can assign a

collection of ‘attributes’ to the Page-Frame

that it points to; for example:

– The P-bit (page is ‘present’) can be used by

the operating system to support its

implementation of “demand paging”

– The W/R-bit can be used to mark a page as

‘Writable’ or as ‘Read-Only’

– The U/S-bit can be used to mark a page as

‘User accessible’ or as ‘Supervisor-Only’

Format of a Page-Directory entry

PAGE-TABLE BASE ADDRESS U W P

P

W

T

P

C

D

0 A

P

S

AVAIL

LEGEND

P = Present (1=yes, 0=no) W = Writable (1 = yes, 0 = no) U = User (1 = yes, 0 = no) A = Accessed (1 = yes, 0 = no)

PWT = Page Write-Through (1=yes, 0 = no) PCD = Page Cache-Disable (1 = yes, 0 = no)

PS = Page-Size (0=4KB, 1 = 4MB)

Violations

• When a task violates the page-attributes of

any Page-Frame, the CPU will generate a

‘Page-Fault’ Exception (interrupt 0x0E)

• Then the operating system’s page-fault

exception-handler gets control and can

take whatever action it deems is suitable

• The CPU will provide help to the OS in

determining why a Page-Fault occurred

Control Register CR

• Whenever a ‘Page-Fault’ is encountered, the

CPU will save the virtual-address that caused

that fault into the CR2 register

• If the CPU was trying to modify the value of an

operand in a ‘read-only’ page, then that operand’s

virtual address is written into CR

• If the CPU was trying to read the value of an operand

in a supervisor-only page (or was trying to fetch-and-

execute an instruction) while CPL=3, the relevant

virtual address will be written into CR

‘ioremap()’ and ‘iounmap()’

• The Linux kernel offers ‘helper functions’

that let modules request modifications to

the kernel’s page-mapping tables

• Examples:

void * ioremap ( phys_addr, length );

adds page-table entries that ‘map’ the region

void iounmap ( void *virt_addr );

remove previously created page-table entries

Multi-CORE CPU

Multiple Logical Processors

CPU

CPU

1 I/O

APIC

LOCAL APIC

LOCAL APIC

Each processor’s Local-APIC contains a 32-bit register (at offset 0x20) known as the Local-APIC Identification Register which has an 8-bit field intended to store that processor’s unique identification-number

reserved processor ID-number

31 24 23 0

‘ioread32()’

• Our module uses the ‘ioread32()’ function

to ‘input’ the current value from one of the

Local-APIC device’s memory-mapped

registers (and could use the companion

function ‘iowrite32()’ to ‘output’ a value to

these device-registers

• (It might be possible on x86 platforms just

to use normal “C” assignment-statements)