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Optimizing Memory Management: Page Tables and Translation Lookaside Buffers (TLB), Slides of Computer Architecture and Organization

Baddi University of Emerging Sciences and TechnologiesComputer Architecture and Organization

The challenges of managing large virtual address spaces and the use of page tables and translation lookaside buffers (tlb) to improve memory access times. It explains the concept of tlb, its format, and its role in translating virtual addresses to physical addresses. It also covers the organization and functionality of tlb in different memory hierarchies.

Typology: Slides

2012/2013

Uploaded on 04/30/2013

patel
patel 🇮🇳

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Optimizing for
Space
•Page Table too big!
–4GB Virtual Address Space ÷ 4 KB page
⇒ 220 (~ 1 million) Page Table Entries
⇒ 4 MB just for Page Table of single process!
•Variety of solutions to tradeoff Page Table size
for slower performance when miss occurs in
TLB
Use a limit register to restrict page table size and let
it grow with more pages,Multilevel page table,
Paging page tables, etc.
(Take O/S Class to learn more)
Docsity.com
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pf5

Partial preview of the text

Download Optimizing Memory Management: Page Tables and Translation Lookaside Buffers (TLB) and more Slides Computer Architecture and Organization in PDF only on Docsity!

Optimizing for

Space

• Page Table too big!

– 4GB Virtual Address Space ÷ 4 KB page

(~ 1 million) Page Table Entries

⇒ 4 MB just for Page Table of single process!

• Variety of solutions to tradeoff Page Table size

for slower performance when miss occurs in

TLB

Use a limit register to restrict page table size and let

it grow with more pages,Multilevel page table,

Paging page tables, etc.

(Take O/S Class to learn more)

How Translate

Fast?

• Problem: Virtual Memory requires two memory

accesses!

– one to translate Virtual Address into Physical Address

(page table lookup)

– one to transfer the actual data (cache hit)

– But Page Table is in physical memory!

• Observation: since there is locality in pages of

data, must be locality in virtual addresses of those

pages!

• Why not create a cache of virtual to physical

address translations to make translation fast?

(smaller is faster)

• For historical reasons, such a “page table cache” is

called a Translation Lookaside Buffer, or TLB

Translation Look-Aside Buffers

• TLB is usually small, typically 32-4,096 entries

• Like any other cache, the TLB can be fully

associative, set associative, or direct mapped

Processor

TLB Cache

Main

Memory

miss

hit

data

hit

miss

Disk

Memory

OS Fault

Handler

page fault/

protection violation

Page

Table

data

virtual

addr.

physical

addr.

Valid Tag^ Data

Page offset

Page offset

Virtual page number

Valid Physical page number

20

Cache index

Data Cache hit

Byte

offset

Dirty (^) Tag

TLB hit

Physical page number

Physical address tag

31 30 29 15 14 13 12 11 10 9 8 3 2 1 0 DECStation 3100/

Virtual Address MIPS R

TLB

Cache

64 entries,

fully

associative

Physical Address

16K entries,

direct

mapped