Output Expressions - Computer Engineering - Solved Exam, Exams of Computer Science

Main points of this past exam are: Output Expressions, Incomplete Circuits, Mixed Logic, Georgia Tech Engineer, Logic Notation, Mixed Logic Notation, Original Implementation, Nand Implementation, Building Blocks, Combination of Inputs

Typology: Exams

2012/2013

Uploaded on 04/08/2013

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ECE 2030 1:00pm Computer Engineering Spring 2001
4 problems, 5 pages Exam One Solution 9 February 2001
1
Problem 1 (3 parts, 30 points) Incomplete Circuits
For each expression below, create a switch level implementation using N and P type switches.
Assume both inputs and their complements are available. Your design should contain no shorts
or floats. Use as few transistors as possible, but do not simplify the expression.
A
B B
A
A B
AB
Outx
A
D
B
A
Outy
C
E
B
C
D E
B
Outz
A
D
A
B
C
C
D
OUTx = BABA โ‹…+โ‹… OUTy = EDCBA โ‹…โ‹…++ )( OUTz = )))((( DCBA +โ‹…+
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4 problems, 5 pages Exam One Solution 9 February 2001

Problem 1 (3 parts, 30 points) Incomplete Circuits For each expression below, create a switch level implementation using N and P type switches. Assume both inputs and their complements are available. Your design should contain no shorts or floats. Use as few transistors as possible, but do not simplify the expression.

A

B B

A

A B

A B

Outx

A

D

B

A

Outy

C

E

B

C

D E

B

Outz

A

D

A

B

C

C

D

OUTx = A โ‹… B + A โ‹… B OUTy = (^) ( A + (^) B + C )โ‹… D โ‹… E OUTz =^ (((^ A^ + B )โ‹… C )+ D )

4 problems, 5 pages Exam One Solution 9 February 2001

Problem 2 (2 parts, 25 points) Mixed Logic In the year 3000, a Georgia Tech engineer opens a millennium time capsule that contains a gate design using mixed logic notation. โ€œGreat use of a common sub-expression!โ€ she exclaims, โ€œBut you should have used NAND gates.โ€ Extract the two output expressions from the circuit below and then reimplement using NAND gates. Determine the transistor savings of the new design. A B C D

E

OUTx

OUTy F

OUTx = (^) A โ‹…( B โ‹… C + D )

OUTy = (^) ( B โ‹… C + D )+ E + F

NAND gate implementation (use correct mixed logic notation) A B C D

E

OUTx

OUTy F

Transistors in original implementation 5 x 4 + 6 x 2 = 32

Transistors in NAND implementation 5 x 4 + 2 x 2 = 24

4 problems, 5 pages Exam One Solution 9 February 2001

Part B (10 points) For the following behavior (in map format), derive a simplified sum of products expression using a Karnaugh Map. Circle and list the prime implicants, indicating which are essential. Then write the simplified SOP expression.

A

A

B B

C

C

C

D

D D

prime implicants

essential? yes no

A D

A B

A B

B D

A D

B D

simplified SOP expression (^) A โ‹… B + B โ‹… D + A โ‹… D or A โ‹… D + A โ‹… B + B โ‹… D

Part C (10 points) For the following behavior (in map format), derive a simplified product of sums expression using a Karnaugh Map. Circle and list the prime implicants, indicating which are essential. Then write the simplified POS expression.

A

A

B B

C

C

C

D

D D

prime implicants

essential? yes no A + D C + D A + C

simplified POS expression (^) ( A + D )โ‹…( A + C )