Exam Solutions for ECE 2030B Computer Engineering Fall 2009 - Problem 1 to 4, Exams of Computer Science

The solutions to exam two for the computer engineering course ece 2030b in fall 2009. The exam covers various topics such as logic gates, number systems, and digital circuits. Students are required to complete problems related to truth tables, input priority, simplified expressions, and 2-input nand implementation using decoders and or gates.

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2012/2013

Uploaded on 04/08/2013

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ECE 2030B 1:00pm Computer Engineering Fall 2009
4 problems, 5 pages Exam Two Solutions 4 March 2009
Problem 1 (4 parts, 24 points) Building Blocks
Part A (8 points) Consider the circuit below. Complete the truth table. Then state what logical
function this circuit implements.
A
BOut
I
0
I
1
I
2
I
3
O
S
1
S
0
O
3
O
2
O
1
O
0
I
1
I
0
En
oops!
A B Out
0 0 1
1 0 0
0 1 0
1 1 1
This wacky circuit is Even Parity (XNOR)
Part B (6 points) Consider the following circuit below. Determine its input priority.
I
3
I
2
I
1
I
0
O
1
O
0
I0I1I2I3V O1O0
0 0 0 0 0 X X
1 0 0 X 1 0 0
X 1 0 X 1 0 1
X X 1 X 1 1 0
0 0 0 1 1 1 1
I2>I1>I0>I3
Part C (4 points) Derive a simplified expression for O1.
O1 =
I2๎‚ƒI0
โ‹…I1
Part D (6 points) Implement a 2-input NAND using a 2-to-4 decoder and a single OR gate
(which may have any number of inputs). Label the inputs A and B, and output A NAND B.
IN
0
O
0
2 to 4
decoder
IN
1
O
1
O
2
O
3
A
B
A NAND B
1
pf3
pf4

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4 problems, 5 pages Exam Two Solutions 4 March 2009

Problem 1 (4 parts, 24 points) Building Blocks Part A (8 points) Consider the circuit below. Complete the truth table. Then state what logical function this circuit implements.

A B Out

I 0

I 1

I 2

I 3

O

O 3 S 1 S 0

O 2

O 1

O 0

I 1

I 0

En (^) oops!

A B Out 0 0 1 1 0 0 0 1 0 1 1 1 This wacky circuit is Even Parity (XNOR) Part B (6 points) Consider the following circuit below. Determine its input priority.

I 3

I 2

I 1

I 0

O 1

O 0

I 0 I 1 I 2 I 3 V O 1 O 0

0 0 0 0 0 X X

1 0 0 X 1 0 0

X 1 0 X 1 0 1

X X 1 X 1 1 0

I 2 > I 1 > I 0 > I 3

Part C (4 points) Derive a simplified expression for O 1. O 1 = I^ 2 ๎‚ƒ I^ 0 โ‹… I^ 1 Part D (6 points) Implement a 2-input NAND using a 2-to-4 decoder and a single OR gate (which may have any number of inputs). Label the inputs A and B , and output A NAND B.

IN 0

O 0 decoder^ 2 to 4 IN 1

O 1 O 2 O 3

A B

A NAND B

4 problems, 5 pages Exam Two Solutions 4 March 2009 Problem 2 (3 parts, 28 points) Number Systems Part A (10 points) Convert the following notations: binary notation decimal notation 110 0 1010. 128+64+8+2 = 202 1010 0100.1000 1 128+32+4+0.5+0.03125 = 164. 111 1100.11 64+32+16+8+4+0.5+0.25 = 124. octal notation hexadecimal notation 4 733.6 1001 1101 1011.1100 = 0x9DB.C 24 .32 01 0100.0110 1000 = 0x14. Part B (12 points) For the 16 bit representations below, determine the most positive value and the step size (difference between sequential values). All answers should be expressed in decimal notation. Fractions (e.g., 3/16ths) may be used. Signed representations are twoโ€™s complement. representation most positive value step size unsigned integer (16 bits). (0 bits) 64K-1^1 signed fixed-point (11 bits). (5 bits) 1023 31/32^ 1/ signed fixed-point (9 bits). (7 bits) 255 127/128^ 1/ signed fixed-point (14 bits). (2 bits) 8K-1/4^ 1/ Part C (6 points) A 34 bit floating point representation has a 24 bit mantissa field, a 9 bit exponent field, and one sign bit.

What is the largest value that can be represented (closest to infinity)? 2^255

What is the smallest value that can be represented (closest to zero)? 2 -

How many decimal significant figures are supported? ___ 7 _____

4 problems, 5 pages Exam Two Solutions 4 March 2009 Problem 4 (3 parts, 24 points) Registers and Latches Part A (8 points) Implement a transparent latch using only inverters and pass gates. Label the inputs In and En , and output Out.

EN

In Out

Part B (10 points) Implement a register below using needed muxes, latches, pass gates, and inverters (all in icon form). Complete the behavior table at right. Recall that the CLK signal indicates a full ฮฆ 1 ฮฆ 2 cycle; so the output should be the value at the end of a cycle (with the given inputs).

In Out

In Out LatchEn In Out LatchEn

WE RE

In0Out In1S

Part C (6 points) Assume the following signals are applied to your register. Draw the output signal Out. Draw a vertical line where In is sampled. Assume Out is initially zero.

WE

In

Out

In WE RE Clk Out

A 0 0 โ†‘โ†“ Z 0

A 1 0 โ†‘โ†“ Z 0

A 0 1 โ†‘โ†“ Q 0

A 1 1 โ†‘โ†“ A