ECE 241โ Lab 13: Pico Arithmetic Logic Unit
Objective
Use VHDL to model a 4-bit ALU for use in the Picoprocessor.
Pre-Lab (5 pts)
At the start of the lab, show the TA your VHDL code for determining the V signal, based upon
the operation and the sign of the result and the operands.
Experiment (15 pts)
Develop a single VHDL component that models the following ALU. Note: An ALU is a
combinational logic circuit. Be sure to use the exact names for your ALU entity ports! All input
and output signals are std_logic_vectors(3 downto 0). An entity and empty architecture are
located here for your benefit.
rega input Data from Register A
regb input Data from Register B
controls input Operational Code (opcode)
alu_out output ALU output
ccr_out output Data for Condition Control Register
The ccr_out signal corresponds to four 1-bit signals, NZVC: (N) alu_out is negative; (Z) alu_out
is zero; (V) overflow occurred under 2โs complement arithmetic; and (C) a carry/borrow
occurred under unsigned arithmetic. You can use VHDL std_logic_vector operations, including
addition (โ+โ) and subtraction (โ-โ). The last two signals (V and C) are only set on arithmetic
operations and are otherwise cleared. Hint: to determine the C signal you will need to perform
five-bit arithmetic with zero-padded operands. This allows you to capture the carry into the msb
of the 5-bit signal.
The ALU supports the following operations.
Instruction Opcode Operation
ADD 0000 alu_out <= rega + regb; update CCR
SUB 0001 alu_out <= rega - regb; update CCR
AND 0010 alu_out <= rega AND regb; update CCR
OR 0011 alu_out <= rega OR regb; update CCR
CMPL 0100 alu_out <= not(rega); update CCR
IN A 0101 alu_out <= rega; update CCR
Verify your design, post-route, through simulation and demonstrate the simulation to the
instructors.
