ECE 241 โ 7 Segment Decoder, Redux
Objective
Investigate the use of VHDL for implementing combinational logic functions.
Pre-Lab (5 pts)
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Bring๎in๎your๎VHDL๎code๎and๎any๎notes๎you๎made๎while๎designing๎it.๎
Experiment (15 pts)
1. Use VHDL concurrent statementsi[1] to implement your binary to seven-segment decoder
(no processes!)
2. Your code will be more readable if you use std_logic_vectors to represent the
hexadecimal inputs instead of std_logic bits.
3. Perform post-synthesis simulation of your design (all 16 combos).ii[2]
4. Download your design to the Digilent board and verify using switches and the 7-segment
display.
Tip: You will need to connect the anode of the 6-segment display to the power supply, VCC. In
the standard_logic library, a logic โ1โ is equivalent to VCC, and a logic โ0โ is equivalent to GND.
Report (5 pts)
Turn in a brief, professional report that describes your design process and results. Comment on
the โefficiencyโ of VHDL compared to schematics. Elaborate on any problems you encountered.
Finally, attach to your report hardcopies of your VHDL, post-synthesis simulation, and the
signed project summary. Remember to include conclusions in your report.
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i[1] You may use concurrent signal assignments with logical operators, conditional signal assignments, or selected
signal assignments. See VHDL examples 4.3, 4.5, and 4.6 from Harris & Harris.
ii[2] You may want to investigate the use of buses (i.e., std_logic_vectors).