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L08 - Pipelining 1
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Pipelining
what Seymour Cray taught the laundry industry
Iāve got
3 months Worth of laundryTo do tonightā¦
Funny, considering thatheās only got one
outfitā¦
Due Thursday: Lab #
modified 2/23/09 10:
L08 - Pipelining 2
6.004 ā Spring 2009
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Forget circuitsā¦ lets solve a āReal Problemā
Device: WasherFunction: Fill, Agitate, SpinWasher
= 30 minsPD Device: DryerFunction: Heat, SpinDryer
= 60 minsPD
INPUT:dirty laundry OUTPUT:6 more weeks
L08 - Pipelining 3
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Total = Washer
PD
= _________ mins
One load at a time
Everyone knows that the realreason that MIT students putoff doing laundry so long is notbecause they procrastinate,are lazy, or even have betterthings to do.The fact is, doing one load at a timeis not smart.
L08 - Pipelining 4
6.004 ā Spring 2009
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Doing N loads of laundry
Hereās how they do laundry atHarvard, the ācombinationalā way.
Total = N*(Washer
)PD
= ____________ mins
N*
(Of course, this is just an urban legend.No one at Harvard actually
does
laundry. The butlers all arrive onWednesday morning, pick up the dirtylaundry and return it all pressed andstarched in time for afternoon tea)
Figure by MIT OpenCourseware.
Step 1: Step 2:
Figure by MIT OpenCourseware.
Image by MIT OpenCourseWare.
Step 1: Step 2: Step 3: Step 4:...
Figure by MIT OpenCourseware.
L08 - Pipelining 5
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Doing N Loadsā¦ the MIT way
MIT students āpipelineāthe laundry process.Thatās why we wait!
Total = N * Max(Washer
, DryerPD
)PD
= ____________ mins
N*
Actually, itās more like N*60 + 30if we account for the startuptransient correctly. When doingpipeline analysis, weāre mostlyinterested in the āsteady stateāwhere we assume we have aninfinite supply of inputs.
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6.004 ā Spring 2009
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Performance Measures
Latency:^ The delay from when an input is established until the outputassociated with that input becomes valid.
(Harvard Laundry = _________ mins)(^
MIT Laundry = _________ mins)
Throughput:^ The
rate
at which inputs or outputs are processed.
(Harvard Laundry = _________ outputs/min)(^
MIT Laundry = _________ outputs/min)
(^90120) 1/901/
Assuming that the washis started as soon aspossible and waits (wet)in the washer until dryeris available.
L08 - Pipelining 7
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Okay, back to circuitsā¦
F G
H
X^
P(X)
For combinational logic:latency = t
,PD
throughput = 1/t
PD.
We canāt get the answer faster, butare we making effective use of ourhardware at all times?
F(X) G(X)P(X)
X^ F & G are āidleā, just holding their outputsstable while H performs its computation
L08 - Pipelining 8
6.004 ā Spring 2009
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Pipelined Circuits
use registers to hold Hās input stable!F G
H
X^
P(X)
15 20
25
Now F & G can be working on input X
i+
while H is performing its computation onX^. Weāve created a 2-stagei^
pipeline
: if we
have a valid input X during clock cycle j,P(X) is valid during clock j+2.
Suppose F, G, H have propagation delays of 15, 20, 25 ns andwe are using ideal zero-delay registers:
latency^45 ______
throughput1/45______
unpipelined
2-stage pipeline
(^50) worse
1/25better
Step 1: Step 2: Step 3:...^ Figure by MIT OpenCourseware.
L08 - Pipelining 13
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Pipeline Example
A
B
C
X Y
2
1
1
0-pipe:1-pipe:2-pipe:3-pipe:
LATENCY
THROUGHPUT
OBSERVATIONS:
- 1-pipeline improves neitherL or T.ā¢ T improved by breaking longcombinational paths,allowing faster clock.ā¢ Too many stages cost L,donāt improve T.ā¢ Back-to-back registers areoften required to keeppipeline well-formed.
2
L08 - Pipelining 14
6.004 ā Spring 2009
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Pipelining Summary
Advantages:
- ^ Allows us to increase thruput, by breaking up longcombinational paths and (hence) increasing clockfrequency
Disadvantages:
- ^ May increase latency... ā ^ Only as good as the weakest link: slowest stepconstrains system thruput.
Isnāt there a way around this āweak linkā problem?
This bottleneckis the onlyproblem
L08 - Pipelining 15
but... but... 3/3/ How can I pipelinea^ clothes dryer???
Aā^ (2-pipe)
Pipelined Components
C
X Y
1
Pipelined systems can behierarchical:
- ^ Replacing a slowcombinational componentwith a k-pipe version mayincrease clock frequency
B^1
3
1
2
4 4-stage pipeline, thruput=
- ^ Must account for newpipeline stages in our plan
L08 - Pipelining 16
6.004 ā Spring 2009
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How do 6.004 Aces do Laundry?
They work around the bottleneck.First, they find a place withtwice as many dryers aswashers.Throughput =
______ loads/min
Latency = ______ mins/load
Step 1: Step 2: Step 3: Step 4:^ Figure by MIT OpenCourseware.
L08 - Pipelining 17
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Back to our bottleneck...
A4 nS
B3 nS
C8 nS D4 nS
E2 nS
F5 nS
T = 1/8nsL = 24ns
Recall our earlier example...
- ^ C ā the slowest component ālimits clock period to 8 ns. ā¢ ^ HENCE throughput limited to1/8ns. We could improve throughput by - ^ Finding a pipelined version of C;OR ... ā¢ ^ interleaving
multiple copies of C!
L08 - Pipelining 18
6.004 ā Spring 2009
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Circuit Interleaving
We can simulate a pipelinedversion of a slowcomponent by replicatingthe critical element andalternate inputs betweenthe various copies.
C^0 D QG D Q
1 0 Cā
D Q^ G
C^1
Xi
C(Xi-
This is a simple2-state FSMthat alternatesbetween 0 and 1on each clock
clk Q
L08 - Pipelining 19
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Circuit Interleaving
We can simulate a pipelinedversion of a slowcomponent by replicatingthe critical element andalternate inputs betweenthe various copies.
C^0 D QG D Q
(^10)
Cā
D Q^ G
C^1
X^ i
C(X^ i-
clk Q
When Q is 1 the lower path iscombinational (the latch isopen), yet the output of theupper path will be enabledonto the input of the outputregister ready for the NEXTclock edge.Meanwhile, the other latchmaintains the input from thelast clock.
C^ odd
Coutput^1
Ceven
Mux output
Codd
āIt acts like a 2-stage pipelineā
L08 - Pipelining 20
6.004 ā Spring 2009
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C^0 D QG D Q
1 0 Cā
D Q^ G
C^1
Xi
x x^
C(Xi-
C^0 D QG D Q
1 0 Cā
D Q^ G
C^1
X^0
C(Xi-
C^0 D QG D Q
1 0 Cā
D Q^ G
C^1
X^1
C(Xi-
C^0 D QG D Q
1 0 Cā
D Q^ G
C^1
X^2
C(X^0
C^0 D QG D Q
1 0 Cā
D Q^ G
C^1
X^3
C(X^1
Circuit Interleaving
Latency = 2 clocks
presented at input, 0
propagates thru upper latch, C
. 0 - ^ Clock period 1: X
presented at input, 1
propagates thru lower latch, C
. C(X 10
) 0
propagates to register inputs. ā¢ Clock period 2: X
presented at input, 2
propagates thru upper latch, C. C
(X^ ) loaded 00
into register, appears at output.
N registersā¦ N-wayinterleave
2-Clock MartinizingN-way interleavingis equivalent toN pipeline Stages...
āIn by t
, out by ti
āi+
L08 - Pipelining 25
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Self-timed Example
a glimpse of an asynchronous, locally-time discipline
Elegant, timing-independent design:
X ā¢ Each component specifies its own time constraintsā¢ Local adaptation to special cases (eg, multiplication by 0)ā¢ Module performance improvements automatically exploitedā¢ Can be made asynchronous (no clock at all!) or synchronous
A^
C
B A(X)
hereās^
ā¦Got it.
L08 - Pipelining 26
6.004 ā Spring 2009
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Control Structure TaxonomySynchronous
Asynchronous
GloballyTimed LocallyTimed
Centralized clockedFSM generates allcontrol signals.
Central control unit tailorscurrent time slice to
current tasks.
Start and Finish signalsgenerated by each major
subsystem, synchronously with global
clock.
Each subsystem takesasynchronous Start,generates asynchronousFinish (perhaps using local
clock).
Easy to design but fixed-sizedinterval can be wasteful (no data-dependencies in timing)
Large systems lead to verycomplicated timing generatorsā¦just say no!
The best way to build largesystems that haveindependently-timed
components.
The ānext big ideaā for the lastseveral decades: a lot of designwork to do in general, but extrawork is worth it in special cases
L08 - Pipelining 27
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Summary
- ^ Latency (L) = time it takes for given input to arrive at output ā¢ ^ Throughput (T) = rate at each new outputs appear ā¢ ^ For combinational circuits: L = t
of circuit, T = 1/LPD
- ^ For K-pipelines (K > 0):
- ^ always have register on output(s) ā¢ ^ K registers on every path from input to output ā¢ ^ Inputs available shortly after clock i, outputs availableshortly after clock (i+K) ā¢ ^ T = 1/(t
PD,REG
of slowest pipeline stage + t
SETUP
^ split slowest pipeline stage(s)
- ^ use replication/interleaving if no further splits possible
^ combinational latency
