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An in-depth exploration of pipelining in computer architecture. It covers the concept of pipelining, its benefits, and the challenges it presents. Recaps, lessons, and explanations of the five stages of r-type and store instructions, as well as the three stages of beq. The document also discusses datapath and data stationary control, and the issues that arise in pipelined design. It concludes with a summary of pipelining and its impact on performance.
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Chapter 6.2 - Pipelining
-^ Sequential laundry takes 6 hours for 4 loads •^ If they learned pipelining, how long would laundry take?
T a s k O r d e r
Time
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Chapter 6.2 - Pipelining
-^ Pipelining doesn’t helplatency of single task, it helpsthroughput of entire workload •^ Pipeline rate limited byslowest pipeline stage •^ Multiple tasks operatingsimultaneously usingdifferent resources •^ Potential speedup = Numberpipe stages •^ Unbalanced lengths of pipestages reduces speedup •^ Time to “fill” pipeline andtime to “drain” it reducesspeedup •^ Stall for Dependences
T a s k O r d e r
Time
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Chapter 6.2 - Pipelining
-^ The five independent functional units in the pipeline datapathare: - Instruction Memory for the Ifetch stage– Register File’s Read ports (bus A and busB) for the Reg/Decstage– ALU for the Exec stage– Data Memory for the Mem stage– Register File’s Write port (bus W) for the Wr stage Clock
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Ifetch
Reg/Dec
Exec
Mem
Wr
1st lw
Ifetch
Reg/Dec
Exec
Mem
Wr
2nd lw
Ifetch
Reg/Dec
Exec
Mem
Wr
3rd lw
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Chapter 6.2 - Pipelining
-^ Ifetch: Instruction Fetch - Fetch the instruction from the Instruction Memory -^ Reg/Dec: Registers Fetch and Instruction Decode •^ Exec: - ALU operates on the two register operands– Update PC -^ Wr: Write the ALU output back to the register file
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Ifetch
Reg/Dec
Exec
Wr
R-type
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Chapter 6.2 - Pipelining
-^ Ifetch: Instruction Fetch - Fetch the instruction from the Instruction Memory -^ Reg/Dec: Registers Fetch and Instruction Decode •^ Exec: Calculate the memory address •^ Mem: Write the data into the Data Memory
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Ifetch
Reg/Dec
Exec
Mem
Store
Wr
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Chapter 6.2 - Pipelining
-^ Ifetch: Instruction Fetch - Fetch the instruction from the Instruction Memory -^ Reg/Dec: - Registers Fetch and Instruction Decode -^ Exec: - compares the two register operand,– select correct branch target address– latch into PC
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Ifetch
Reg/Dec
Exec
Mem
Beq^
Wr
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Chapter 6.2 - Pipelining
these addresses are octal
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Chapter 6.2 - Pipelining
Exec
Reg.File
MemAcces
s Data
Mem
RegFile Inst. MemIR
Decode
MemCtrl
WBCtrl M
rs^ rt
im
10
lw^
r1, r2(35) 14
addI
r2, r2, 3 20
sub^
r3, r4, r 24
beq^
r6, r7, 100 30
ori^
r8, r9, 17 34
add^
r10, r11, r 100 and
r13, r14, 15
IF
Next PC
n^
n^
n^
n
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Chapter 6.2 - Pipelining
Exec
Reg.File
MemAcces
s Data
Mem
r2 B
RegFile Inst. MemIR
Decode
MemCtrl
WBCtrl M
2 rt
10
lw^
r1, r2(35) 14
addI^
r2, r2, 3 20
sub^
r3, r4, r 24
beq^
r6, r7, 100 30
ori^
r8, r9, 17 34
add^
r10, r11, r 100 and
r13, r14, 15
lw r
addI r2, r2, 3
Next PC
n^
n
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Chapter 6.2 - Pipelining
Exec
Reg.File
MemAcces
s Data
Mem
r2 B
r2+
RegFile Inst. MemIR
Decode
MemCtrl
WBCtrl M
10
lw^
r1, r2(35) 14
addI^
r2, r2, 3 20
sub^
r3, r4, r 24
beq^
r6, r7, 100 30
ori^
r8, r9, 17 34
add^
r10, r11, r 100 and
r13, r14, 15
lw r
sub r3, r4, r
addI r2, r2, 3
Next PC
n
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Chapter 6.2 - Pipelining
Exec
Reg.File
MemAcces
s Data
Mem
r6 r
r2+
RegFile Inst. MemIR
Decode
MemCtrl
WBCtrl
r1=M[r2+35]
9 xx
10
lw^
r1, r2(35) 14
addI^
r2, r2, 3 20
sub^
r3, r4, r 24
beq^
r6, r7, 100 30
ori^
r8, r9, 17 34
add^
r10, r11, r 100 and
r13, r14, 15
beq
addI r
sub r3 r4-r
100
ori r8, r9 17
Next PC
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Chapter 6.2 - Pipelining
Exec
Reg.File
MemAcces
s Data
Mem
RegFile Inst. MemIR
Decode
MemCtrl
WBCtrl^10
lw^
r1, r2(35) 14
addI^
r2, r2, 3 20
sub^
r3, r4, r 24
beq^
r6, r7, 100 30
ori^
r8, r9, 17 34
add^
r10, r11, r 100 and
r13, r14, 15
WBM EX ID
Next PC
Fill it in yourself!
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Chapter 6.2 - Pipelining
Exec
Reg.File
MemAcces
s Data
Mem
RegFile Inst. MemIR
Decode
MemCtrl
WBCtrl^10
lw^
r1, r2(35) 14
addI^
r2, r2, 3 20
sub^
r3, r4, r 24
beq^
r6, r7, 100 30
ori^
r8, r9, 17 34
add^
r10, r11, r 100 and
r13, r14, 15
WB^ M
Next PC
Fill it in yourself!
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Chapter 6.2 - Pipelining
-^ Avoid
Mem WB
Ex^
Mem
RAW Data Hazard
WAW Data Hazard
Ex
WAR Data Hazard
Mem
Mem WB
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