Understanding Pipelining and Hazards in Computer Architecture, Slides of Computer Science

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Pipelining - II

Revisiting Pipelining Lessons

• Pipelining doesn’t help

latency of single task, it

helps throughput of

entire workload

• Pipeline rate limited by

slowest pipeline stage

• Multiple tasks operating

simultaneously using

different resources

• Potential speedup =

Number pipe stages

• Unbalanced lengths of

pipe stages reduces

speedup

• Time to “fill” pipeline and

time to “drain” it reduces

speedup

• Stall for Dependences

A

B

C

D

6 PM 7 8

T a s k O r d e r

Time

Control Signals for existing Datapath

The Right to Left Control can lead to hazards

M U X P C ADD Registers ADD ADD Sign Extend 4 Instruction Memory Address Instruction Read Reg Read Reg Write Reg Write Data Read Data Read Data2 MU X Data Memory Address Write Data Read Data M U X IF: Instruction Fetch ID: Instruction Decode/ register file read EX: Execute/address calculation MEM: Memory Access^ WB: Write back 16 32 Shift left 2 Zero

Place registers between each step

M U X P C ADD Registers ADD ADD Sign Extend 4 Instruction Memory Address Instruction Read Reg Read Reg Write Reg Write Data Read Data Read Data2 MU X Data Memory Address Write Data Read Data M U X 16 32 Shift left 2 Zero IF/ID ID/EX EX/MEM MEM/WB

Start: Fetch 10

Exec

Reg. File

Mem Acces

s

Data Mem

A

B

S

Reg File

IR

Inst. Mem

D

Decode

Mem

Ctrl

WB

Ctrl

M

rs rt

im

10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r 100 and r13, r14, 15

IF

PC

Next PC

n n n n

Fetch 14, Decode 10

Exec

Reg. File

Mem Acces

s

Data Mem

A

B

S

Reg File

IR

Inst. Mem

D

Decode

Mem

Ctrl

WB

Ctrl

M

2 rt

im

10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r 100 and r13, r14, 15 lw r1, r2(35)

ID

IF

PC

Next PC

n n n

Fetch 24, Decode 20, Exec 14, Mem 10

Exec

Reg. File

Mem Acces

s

Data Mem

r

B

r2+

Reg File

IR

Inst. Mem

D

Decode

Mem

Ctrl

WB

Ctrl

M

10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r 100 and r13, r14, 15 lw r sub r3, r4, r5^ addI r2, r2, 3

ID

IF

EX

M

PC

Next PC

n

Fetch 30, Dcd 24, Ex 20, Mem 14, WB 10

Exec

Reg. File

Mem Acces

s

Data Mem

r

r

Reg File r2+

IR

Inst. Mem

D

Decode

Mem

Ctrl

WB

Ctrl

M[r2+35]

10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r 100 and r13, r14, 15 lw r beq r6, r7 100 sub r3^ addI r

ID

IF

EX

M

WB

PC

Next PC

Pipelining Load Instruction

• The five independent functional units in the pipeline datapath

are:

– Instruction Memory for the Ifetch stage

– Register File’s Read ports (bus A and busB) for the

Reg/Dec stage

– ALU for the Exec stage

– Data Memory for the Mem stage

– Register File’s Write port (bus W) for the Wr stage

Clock Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 1st lw Ifetch Reg/Dec Exec Mem Wr 2nd lw Ifetch Reg/Dec Exec Mem Wr 3rd lw Ifetch Reg/Dec Exec Mem Wr

Pipelining the R Instruction

• Ifetch: Instruction Fetch

– Fetch the instruction from the Instruction Memory

• Reg/Dec: Registers Fetch and Instruction Decode

• Exec:

– ALU operates on the two register operands

– Update PC

• Wr: Write the ALU output back to the register file

Cycle 1 Cycle 2 Cycle 3 Cycle 4 R-type Ifetch Reg/Dec Exec Wr

Important Observations

• Each functional unit can only be used once per

instruction

• Each functional unit must be used at the same

stage for all instructions:

– Load uses Register File’s Write Port during its 5th

stage

– R-type uses Register File’s Write Port during its

4th stage

Load Ifetch Reg/Dec Exec Mem Wr

R-type Ifetch Reg/Dec Exec Wr

Solution

• Delay R-type’s register write by one cycle:
  • Now R-type instructions also use Reg File’s write port at Stage 5
  • Mem stage is a NOOP stage: nothing is being done. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Ifetch Reg/Dec Mem Wr R-type Ifetch Reg/Dec Mem Wr Load Ifetch Reg/Dec Exec Mem Wr R-type Ifetch Reg/Dec Mem Wr R-type Ifetch Reg/Dec Mem Wr R-type Ifetch Reg/Dec Exec^ Mem Wr Exec Exec Exec Exec

Datapath (With Pipeline)

IR <- Mem[PC]; PC <– PC+4; A <- R[rs]; B<– R[rt] S <– A + B; R[rd] <– M; S <– A + SX; M <– Mem[S] R[rd] <– M; S <– A or ZX; R[rt] <– M; S <– A + SX; Mem[S] <- B if Cond PC < PC+SX; M <– S

Exec

Reg. File

Mem Acces

s

Data Mem

A

B

S

Reg File

Equal

PC

Next PC

IR

Inst. Mem

D

M

M <– S

Mem Structural Hazard and Solution

I

n

s

t

r.

O

r

d

e

r

Time (clock cycles)

Load Instr 1 Instr 2 Instr 3 Instr 4

ALU

Mem Reg Mem Reg ALU Mem Reg Mem Reg ALU Mem Reg Mem Reg ALU Reg Mem Reg ALU Mem Reg Mem Reg