Practice Exam - System Architecture | CMSC 411, Exams of Computer Science

Material Type: Exam; Class: SYSTM ARCHITECTURE; Subject: Computer Science; University: University of Maryland; Term: Spring 2009;

Typology: Exams

Pre 2010

Uploaded on 07/30/2009

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CMSC 411 Practice Exam 1
General instructions.
Be complete, yet concise. You may leave arithmetic expressions in any form that a calculator could evaluate.
1. CPU performance
Suppose we have the following instruction mix and clock cycles per instruction.
Instruction Frequency Cycles
ALU operations 30% 1
Load 20% 2
Store 10% 2
Branches 20% 3
Floating point operations 20% 5
(a) What is the overall CPI of this machine?
(b) If the CPU runs at 750MHz, what is the MIPS rating of this machine? For this question, count
floating point operations in the MIPS rating.
(c) Consider improving this computer’s performance by enhancing the speed of the floating point
instructions. What is the best possible overall speedup that we could obtain?
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CMSC 411 Practice Exam 1

General instructions. Be complete, yet concise. You may leave arithmetic expressions in any form that a calculator could evaluate.

  1. CPU performance Suppose we have the following instruction mix and clock cycles per instruction.

Instruction Frequency Cycles ALU operations 30% 1 Load 20% 2 Store 10% 2 Branches 20% 3 Floating point operations 20% 5

(a) What is the overall CPI of this machine? (b) If the CPU runs at 750MHz, what is the MIPS rating of this machine? For this question, count floating point operations in the MIPS rating. (c) Consider improving this computer’s performance by enhancing the speed of the floating point instructions. What is the best possible overall speedup that we could obtain?

  1. Speedup

Two enhancements, E 1 and E 2 , with the following speedups are proposed for a new architecture:

Speedup 1 = 10

Speedup 2 = 5

Only one of the enhancements is usable at any point in time (maybe because they use some of the same hardware).

(a) If E 1 can be used 20% of the time and E 2 can be used 10% of the time, what would be the overall speedup?

(b) If the percentage of time that E 1 can be used decreased to 15%, what percentage of the time would the use of E 2 have to be to get the same overall speedup as in part (a)?

(c) Supose we are free to choose between E1 or E2, whenever we want (the percentages of time for using E1 or E2 can be varied as desired, but in total cannot be more than 100% of the time). What would be the maximum achievable overall speedup?

  1. Basic pipelining

Consider the following MIPS code:

I1: DADD R1, R5, R

I2: DADD R3, R1, R

I3: SD R5, 10(R1)

I4: DADD R5, R1, R

Suppose we have the simple MIPS 5-stage pipeline from Appendix A in the book (and every instruc- tion must go through all 5 stages).

(a) Fill in the first pipeline table showing execution of the instructions assuming that no forwarding is available, then fill out the second table assuming that forwarding is available in the pipeline wherever it is needed. Without forwarding 1 2 3 4 5 6 7 8 9 10 11 12 13 I1 IF ID EX MEM WB I I I

With forwarding 1 2 3 4 5 6 7 8 9 10 11 12 13 I1 IF ID EX MEM WB I I I (b) Show and classify all the potential data hazards (RAW, WAR, WAW). Which of the potential RAW data hazards are eliminated because of forwarding?