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Practice Midterm, CSE 240A, Fall 2006
Problem #1 : A program’s execution can be broken up into 2 parts, floating point instructions and integer instructions. Assume we execute a program on two processors A and B. The only difference between processors A and B is that integer instructions execute 5 times faster on processor B (compared to processor A). If the same program is run on processor A and B, and the program run on processor B is 1.5 times faster than on processor A, what percent of the program’s execution on processor A is due to the integer instructions? (Write all calculations down to receive full credit)
Problem #2 : Assume the pipeline for this problem is a single issue in-order 8 stage pipeline (Fetch, Decode1, Decode2, Decode3, Execute1, Execute2, Memory, Writeback). Branch condi- tions are done executing at the end of Execute2. So, if the branch was mispredicted, the program counter will be corrected at the end of Execute2 for the next cycle fetch. When executing a program X, assume 20% of the instructions are branches, and 60% of the branches are taken.
Assume a processor that always predicts branches as not-taken during fetch. What is the branch misprediction penalty? What is CPI with branch stalls? (Show all equations and calculations to receive credit, and clearly label where the stalls are coming from in the equations.)
Problem #4 : We are considering adding a new addressing mode to MIPS. In this new ad- dressing mode, loads and stores have the following format:
LD R1, 0(R2,R3)
This is essentially a variant of the displacement addressing mode but here the address is given by R2 + R3 + displacement, with the displacement being 11 bits. Using this instruction, we can replace the following sequence of instructions:
ADD R1, R1, R LD Rd, 0(R1)
with an instruction of the new format. Remember that this also works for store instruction. Assume that the instruction mix is 15% conditional branches, 20% loads, 5% stores and the rest being ALU instructions.
Part (a), Assume that the new addressing mode can be used for 10% of loads and 15% of stores. What is the ratio of instruction count on the MIPS with new addressing mode compared to the original MIPS?
Part (b), If the addressing mode lengthens the clock cycle by 5%, which machine will be faster and by how much?
