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Practice Problem Set 1 for CS433g: Computer System Organization - Prof. Josep Torrellas, Assignments of Computer Architecture and Organization

University of Illinois - Urbana-ChampaignComputer Architecture and Organization
Prof. Josep Torrellas

Practice problem set 1 for the cs433g course on computer system organization, offered in fall 2005. It includes 6 questions related to computer system organization, amdahl's law, instruction set architectures, and memory transfer. The questions cover topics such as speedup, enhanced mode, clock cycle time, and autoincrement addressing mode.

Typology: Assignments

Pre 2010

Uploaded on 03/11/2009

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CS433g: Computer System Organization – Fall 2005
Practice Problem Set 1
Question 1
Assume that we make an enhancement to a computer that improves some mode of execution by a
factor of 10. Enhanced mode is used 60% of the time, measured as a percentage of the execution
time when the enhanced mode is in use. Recall that Amdahl’s Law depends on the fraction of the
original un-enhanced execution time that could make use of enhanced mode. Thus, we cannot
directly use this 60% measurement to compute speedup with Amdahl’s Law.
a. What is the speedup we have obtained from the enhanced mode (relative to the original)?
b. What percentage of the original execution time has been converted to enhanced mode?
Question 2
Three enhancements with the following speedup are proposed for a new architecture (assume
they apply to non-overlapping parts of the execution):
Speedup1 = 30
Speedup2 = 25
Speedup3 = 15
a. If enhancements 1 and 2 are each usable for 30% of the time, what fraction of the time
must enhancement 3 be used to achieve an overall speedup of 10?
b. Assume the three enhancements are respectively used over 40%, 30%, and 20% of the
original execution. Now consider the enhanced version. For what fraction of the new
execution time is no enhancement in use?
c. Assume for some benchmark, enhancement 1 is used for 15% of the original execution,
enhancement 2 is used for 20% of the original execution, and enhancement 3 is used for
65% of the original execution. We want to maximize performance. If only one
enhancement can be implemented, which should it be? If two enhancements can be
implemented, which should be chosen?
pf3
pf4

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CS433g: Computer System Organization – Fall 2005 Practice Problem Set 1

Question 1

Assume that we make an enhancement to a computer that improves some mode of execution by a factor of 10. Enhanced mode is used 60% of the time, measured as a percentage of the execution time when the enhanced mode is in use. Recall that Amdahl’s Law depends on the fraction of the original un-enhanced execution time that could make use of enhanced mode. Thus, we cannot directly use this 60% measurement to compute speedup with Amdahl’s Law. a. What is the speedup we have obtained from the enhanced mode (relative to the original)? b. What percentage of the original execution time has been converted to enhanced mode?

Question 2

Three enhancements with the following speedup are proposed for a new architecture (assume they apply to non-overlapping parts of the execution):

Speedup 1 = 30 Speedup 2 = 25 Speedup 3 = 15

a. If enhancements 1 and 2 are each usable for 30% of the time, what fraction of the time must enhancement 3 be used to achieve an overall speedup of 10? b. Assume the three enhancements are respectively used over 40%, 30%, and 20% of the original execution. Now consider the enhanced version. For what fraction of the new execution time is no enhancement in use? c. Assume for some benchmark, enhancement 1 is used for 15% of the original execution, enhancement 2 is used for 20% of the original execution, and enhancement 3 is used for 65% of the original execution. We want to maximize performance. If only one enhancement can be implemented, which should it be? If two enhancements can be implemented, which should be chosen?

Consider the following types of instruction set architectures:

  1. Accumulator: All operations occur between a single register and memory location. LOAD A – loads the accumulator with the contents of memory location A. STORE A – stores the contents of accumulator into memory location A, leaving the accumulator contents intact. ADD A – adds the contents of memory location A to the accumulator.
  2. Stack: All operations occur on top of the stack. Push and pop are the only instructions that access memory. ALU operations implicitly use the top two elements of the stack and replace them with the result. PUSH A – Pushes the contents of the memory location A on the top of the stack POP A – Removes the contents at the top of the stack and stores it in the memory location A. ADD – Adds together the top two elements on the stack, removes both the elements from the stack, and stores the computed result on the top of the stack.
  3. Load-store: All ALU operations occur in registers and register-to-register instructions have three register names per instruction. Load and Store are the only instructions that access memory directly. LOAD R1, A – Loads the contents of memory location A into the register R1. STORE A, R1 – Stores the contents of register R1 into the memory location A. ADD R1, R2, R3 – Adds the contents of register R2 and R3 and stores the result in register R1.

We have the following high-level code sequence: C = A + B D = C + A

a. Write the assembly code sequence for the above code sequence for the three instruction set architectures. You can use the assembly language mnemonics given above. The assembly code you write must use as few instructions as possible.

b. Assume that every access to memory for data reads/writes 4 bytes. How many bytes of data are transferred between memory and processor for each of the three ISAs in the code sequence (show the data bytes transferred for each instruction in the code)? Which architecture transfers the least amount of data between memory and processor?

Compute the effective CPI for MIPS using figure 2.32 of the textbook. Suppose we have made the following measurements of average CPI for instructions:

Instruction Clock cycles

  • All ALU instructions 1.
  • Loads -stores 1.
  • Conditional Branches o Taken 2. o Not Taken 1.
  • Jumps 1.

Assume that 60% of conditional branches are taken and that all instructions in the ‘other’ category of Figure 2.32 of the textbook are ALU instructions. Use the average of the instruction frequencies of gap and gcc to obtain the instruction mix. Conditional move and load immediate should be treated as ALU instructions.