CS433g: Computer System Organization
Practice Set for Chapter 4 – Part 1
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CREDIT for this homework.
Problem 1
Consider a loop that implements the vector computation Y = aX + Y (commonly known
as DAXPY). Here is the code:
foo:
L.D F2, 0(R1) ; load X(i)
MULT.D F4, F2, F0 ; multiply a*X(i)
L.D F6, 0(R2) ; load Y(i)
ADD.D F6, F4, F6 ; add a*X(i) + Y(i)
S.D 0(R2), F6 ; store Y(i)
DADDUI R1, R1, #8 ; increment Y index
DADDUI R2, R2, #8 ; increment X index
DSGTUI R3, R1, #800 ; set if greater than (test if done)
BEQZ R3, foo ; loop if not done
Consider a VLIW processor and make the following assumptions:
• All integer operations, all loads, and all stores spend 1 cycle in EX
• All FP operations spend 4 cycles in EX. The FP units are fully pipelined.
• Ignore branch delay.
• Assume data forwarding as necessary.
• The VLIW processor can issue one integer (or branch) operation, two memory
operations, and two FP operations every cycle.
• For load and store operations, both effective address calculation and memory
access occur in the EX stage (i.e. the data is written in the EX stage). Therefore,
the pipeline is IF/ID/EX/WB).
You are required to unroll the above loop body four times and then schedule the unrolled
loop for the above VLIW processor, eliminating as many stalls as possible. Show the
unrolled loop as part of your solution. For the final answer, indicate which operation will
issue (to its execution unit) in each clock cycle by filling in the table given below.
Calculate the CPI for the four iterations.
Issue Cycle Memory
reference 1 Memory
reference 2 FP operation
1 FP operation
2 Integer
op/branch
1
2
3
