Download PrepIQ 16ELECA5 Electronics Bundle Ultimate Exam and more Exams Technology in PDF only on Docsity!
Question 1. Which of the following best describes an intrinsic semiconductor? A) A semiconductor doped with donor atoms B) A pure semiconductor with no impurity atoms C) A semiconductor doped with acceptor atoms D) A semiconductor with a built-in electric field Answer: B Explanation: An intrinsic semiconductor is a pure material (e.g., silicon) without intentional dopants, so its electrical properties arise solely from its own crystal structure. Question 2. In an n-type semiconductor, the majority carriers are: A) Holes B) Electrons C) Both holes and electrons equally D) Ions Answer: B Explanation: Doping silicon with donor atoms adds extra electrons, making electrons the majority carriers in n-type material. Question 3. The Fermi level in an intrinsic semiconductor lies: A) Near the conduction band B) Near the valence band C) Exactly at the middle of the band gap D) Outside the band gap Answer: C Explanation: In an intrinsic semiconductor, the probability of occupancy is equal for electrons and holes, placing the Fermi level at the midpoint of the band gap. **Question 4. Which junction forms the basis of a Zener diode’s regulation function? **
A) Forward-biased p-n junction B) Reverse-biased p-n junction operating in breakdown C) Schottky barrier D) Metal-oxide-semiconductor interface Answer: B Explanation: Zener diodes are operated in reverse bias where the p-n junction undergoes controlled breakdown (Zener or avalanche) to maintain a constant voltage. Question 5. A Schottky diode differs from a regular pn-junction diode primarily because: A) It uses a metal-semiconductor junction B) It has a larger depletion region C) It operates only in forward bias D) It requires a Zener breakdown voltage Answer: A Explanation: Schottky diodes employ a metal-semiconductor (metal-n-type) junction, giving them lower forward voltage drop and faster switching. Question 6. In a varactor diode, the capacitance varies with: A) Temperature only B) Forward bias voltage C) Reverse bias voltage D) Light intensity Answer: C Explanation: A varactor (variable-reactance) diode is reverse-biased; the depletion width changes with reverse voltage, altering the junction capacitance. Question 7. The output of a half-wave rectifier consists of: A) Both positive and negative half-cycles
C) Increases the signal’s frequency D) Provides power gain Answer: B Explanation: A clamping circuit adds a DC level to the entire waveform, shifting it up or down while preserving its peak values. Question 11. In a common-emitter BJT configuration, the phase relationship between input base voltage and output collector voltage is: A) In-phase B) 180° out of phase C) 90° out of phase D) No fixed relationship Answer: B Explanation: The common-emitter stage inverts the signal; an increase in base voltage leads to an increase in collector current, causing a voltage drop across the collector resistor. Question 12. The purpose of biasing a BJT is to: A) Increase the transistor’s breakdown voltage B) Set a stable operating point (Q-point) regardless of temperature variations C) Reduce the collector resistance D) Convert the transistor to a diode Answer: B Explanation: Proper biasing establishes a quiescent operating point that remains stable over temperature and device parameter changes. Question 13. The stability factor (S) of a BJT bias circuit should be: A) As high as possible B) Exactly equal to 1 C) As low as possible
D) Equal to the transistor’s β Answer: C Explanation: A low stability factor indicates that the Q-point is less sensitive to variations in β and temperature, improving circuit reliability. Question 14. In an N-channel enhancement MOSFET, the device turns on when: A) Gate-source voltage is negative B) Gate-source voltage is zero C) Gate-source voltage exceeds the positive threshold voltage D) Drain-source voltage exceeds the breakdown voltage Answer: C Explanation: An enhancement MOSFET requires a positive gate-source voltage above its threshold to create a conductive channel. Question 15. The primary difference between a JFET and a depletion-mode MOSFET is that: A) JFETs are always enhancement mode B) JFETs use a reverse-biased p-n junction to control current C) MOSFETs cannot be used in analog circuits D) JFETs have a metal gate Answer: B Explanation: A JFET’s channel is controlled by the reverse-biased p-n junction (gate-source), whereas a depletion MOSFET uses an insulated gate. Question 16. An SCR (Silicon Controlled Rectifier) is triggered into conduction by: A) Applying a forward voltage across its terminals B) Applying a reverse voltage across its terminals C) A gate current pulse while forward-biased
Answer: B Explanation: In saturation, (g_m = \frac{2I_D}{V_{GS} - V_{TH}}), reflecting how drain current changes with gate voltage. Question 20. A cascode amplifier combines: A) Two common-source stages in series B) A common-emitter stage with an emitter-follower C) A common-base stage followed by a common-emitter stage D) A differential pair with a current mirror load Answer: C Explanation: The cascode uses a common-base stage (high output resistance) cascaded with a common-emitter stage (high gain), improving bandwidth and reducing Miller effect. Question 21. Negative feedback in an amplifier typically results in: A) Increased gain and higher distortion B) Decreased gain, increased bandwidth, and reduced distortion C) No change in input impedance D) Unstable operation Answer: B Explanation: Negative feedback reduces overall gain but linearizes the response, widens bandwidth, and improves input/output impedance. Question 22. The ideal op-amp has an input bias current of: A) 0 A B) 1 mA C) 10 μA D) 100 μA Answer: A
Explanation: In the ideal model, the op-amp draws no input current, leading to infinite input impedance. Question 23. In a summing amplifier using an op-amp, the output voltage is: A) The product of all input voltages B) The sum of the input voltages multiplied by a common gain factor C) The average of the input voltages D) Independent of the input voltages Answer: B Explanation: A summing amplifier produces (V_{out} = -R_f\left(\frac{V_1}{R_1} + \frac{V_2}{R_2}+...\right)); each input contributes proportionally. Question 24. An op-amp integrator’s output voltage is proportional to: A) The instantaneous input voltage B) The derivative of the input voltage C) The integral of the input voltage over time D) The square of the input voltage Answer: C Explanation: An integrator outputs (V_{out} = -\frac{1}{RC}\int V_{in}dt), performing mathematical integration. Question 25. A Schmitt trigger is characterized by: A) A single threshold voltage B) Two distinct threshold voltages causing hysteresis C) Linear amplification of small signals D) No gain Answer: B Explanation: The Schmitt trigger provides positive feedback, creating two separate switching points (upper and lower thresholds) that prevent noise-induced false triggering.
Question 29. In Boolean algebra, the expression (A + \overline{A}B) simplifies to: A) (A + B) B) (\overline{A} + B) C) (A) D) (B) Answer: A Explanation: Using the absorption law: (A + \overline{A}B = A + B). Question 30. The Gray code has the property that adjacent numbers differ by: A) Two bits B) One bit only C) All bits D) No bits (identical) Answer: B Explanation: Gray code is designed so that successive values change only a single bit, reducing transition errors. Question 31. A 4-to-1 multiplexer requires how many select lines? A) 1 B) 2 C) 3 D) 4 Answer: B Explanation: (2^n = 4) gives (n = 2) select lines to choose among four inputs. Question 32. In a binary adder, the carry-out of the least-significant bit (LSB) is generated by:
A) An XOR gate only B) An AND gate only C) An OR gate only D) Both AND and XOR gates in a full-adder cell Answer: D Explanation: A full-adder uses XOR for sum and AND/OR logic to produce the carry-out. Question 33. The Boolean expression for a 2-input NAND gate is: A) (Y = A \cdot B) B) (Y = \overline{A + B}) C) (Y = \overline{A \cdot B}) D) (Y = A + B) Answer: C Explanation: NAND is the complement of the AND operation. Question 34. A priority encoder with 8 inputs produces a 3-bit binary code. If inputs D4 and D6 are both high, the output will represent: A) Input 4 (binary 100) B) Input 6 (binary 110) C) Input 5 (binary 101) D) Invalid condition Answer: B Explanation: The highest-order active input (D6) takes precedence, so the encoder outputs the code for 6. Question 35. A JK flip-flop toggles its output when: A) J=0, K= B) J=0, K=
D) Generating clock signals Answer: C Explanation: SIPO receives serial bits and presents the accumulated word on parallel outputs after the required number of clock cycles. Question 39. Which memory type is non-volatile and can be electrically erased and reprogrammed? A) RAM B) ROM C) EPROM D) DRAM Answer: C Explanation: EPROM (Erasable Programmable ROM) retains data without power and can be erased by UV exposure and reprogrammed electrically. Question 40. In a microprocessor, the Program Counter (PC) holds: A) The address of the next instruction to be fetched B) The current data being processed C) The status flags of the ALU D) The address of the currently executing instruction Answer: A Explanation: The PC points to the memory location of the next instruction to be fetched from program memory. Question 41. Which 8085 instruction transfers the accumulator content to a memory location pointed by the HL pair? A) MOV A, M B) STA addr C) STAX B D) LDA addr
Answer: C Explanation: STAX B stores the accumulator into the memory location addressed by the BC pair; STAX D does the same for DE. For HL, the instruction is STAX H (not listed), but among options, STAX B is the only store-accumulator-to-register-pair instruction, illustrating the concept of register-pair addressing. Question 42. In 8086 architecture, the segment registers are used to: A) Perform arithmetic operations B) Define the base address for different memory areas (code, data, stack, extra) C) Store immediate data D) Generate clock signals Answer: B Explanation: Segment registers (CS, DS, SS, ES) provide the high-order 16 bits of a 20 - bit address, allowing the CPU to access up to 1 MB of memory. Question 43. The 8085’s INX H instruction performs which operation? A) Increment the contents of the H register only B) Increment the 16-bit HL register pair by 1 C) Exchange the contents of H and L D) Decrement the HL pair Answer: B Explanation: INX H adds one to the combined HL register pair, effectively advancing a memory pointer. Question 44. In I/O-mapped I/O, the address lines are used to: A) Select memory locations only B) Select peripheral devices directly, separate from memory address space C) Decode both memory and I/O simultaneously D) Provide power to the peripherals Answer: B
Question 48. Frequency modulation (FM) is less susceptible to: A) Amplitude noise B) Phase noise C) Frequency drift D) Bandwidth limitations Answer: A Explanation: FM encodes information in frequency variations, so amplitude variations (noise) have little effect on demodulated signal. Question 49. In Pulse Code Modulation (PCM), the sampling frequency must be at least: A) Twice the highest signal frequency (Nyquist rate) B) Equal to the highest signal frequency C) One-third of the highest signal frequency D) Unrelated to signal frequency Answer: A Explanation: According to the Nyquist theorem, the sampling rate must be ≥ 2 × bandwidth to avoid aliasing. Question 50. Differential PCM (DPCM) improves upon PCM by: A) Using larger quantization levels B) Encoding the difference between successive samples instead of absolute values C) Removing the need for a clock signal D) Transmitting only the carrier Answer: B Explanation: DPCM reduces redundancy by sending the sample differences, allowing lower bit rates for similar quality. Question 51. In ASK (Amplitude Shift Keying), the information is conveyed by:
A) Varying the carrier frequency B) Varying the carrier phase C) Varying the carrier amplitude D) Varying the carrier polarity Answer: C Explanation: ASK changes the amplitude of the carrier to represent binary symbols. Question 52. Quadrature Amplitude Modulation (QAM) combines which two modulation schemes? A) AM and FM B) PSK and ASK C) FSK and PSK D) FM and PM Answer: B Explanation: QAM modulates both amplitude (ASK) and phase (PSK) to create multiple constellation points. Question 53. The VSWR (Voltage Standing Wave Ratio) on a transmission line is defined as: A) The ratio of forward to reflected power B) (1 + |Γ|)/(1 – |Γ|) where Γ is the reflection coefficient C) The ratio of line impedance to load impedance D) The ratio of line length to wavelength Answer: B Explanation: VSWR quantifies mismatch; Γ is the magnitude of the reflection coefficient. Question 54. The Smith chart is primarily used for: A) Designing digital filters B) Visualizing impedance transformations and matching in the complex plane
Answer: C Explanation: For causal sequences, the ROC lies outside the outermost pole (| z| > p_max). Question 58. In a discrete-time system, the frequency response is periodic with period: A) 2π radians/sample B) π radians/sample C) 4π radians/sample D) No periodicity Answer: A Explanation: Discrete-time Fourier Transform (DTFT) repeats every 2π rad/sample. Question 59. The impulse response h(t) of an LTI system fully determines: A) Only the system’s stability B) Only its frequency response C) Both its time-domain and frequency-domain behavior D) Only its initial conditions Answer: C Explanation: Convolution with h(t) yields output for any input; its Fourier transform gives the frequency response. Question 60. A band-limited signal with maximum frequency (f_{max}=5) kHz must be sampled at a minimum rate of: A) 5 kHz B) 10 kHz C) 7.5 kHz D) 2 kHz Answer: B
Explanation: Nyquist rate = 2 × (f_{max}) = 10 kHz. Question 61. Aliasing occurs when: A) The sampling frequency is higher than the Nyquist rate B) The sampling frequency is lower than twice the signal’s highest frequency component C) The signal is band-limited D) The analog-to-digital converter has infinite resolution Answer: B Explanation: Insufficient sampling causes higher-frequency components to fold into lower frequencies, creating aliasing. Question 62. In a digital communication system, the bit error rate (BER) of a BPSK signal over an AWGN channel is primarily a function of: A) Bandwidth only B) Signal-to-noise ratio (SNR) per bit C) Carrier frequency D) Modulation index Answer: B Explanation: BER for BPSK depends on (E_b/N_0); higher SNR yields lower BER. Question 63. In a 4-bit binary-coded decimal (BCD) representation, the decimal number 9 is encoded as: A) 1001 B) 0110 C) 1111 D) 0010 Answer: A Explanation: BCD uses 4 bits per decimal digit; 9 is 1001.
