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ECE 463: Advanced Microprocessor Design
ECE 521: Computer Design and Technology
Problem Set 2
Friday, March 3, 2006
Problems 1, 3, and 5 will be graded. There are 70 points on these problems. Note: You must do
all the problems, even the non-graded ones. If you do not do some of them, half as many points
as they are worth will be subtracted from your score on the graded problems.
Problem 1. (15 points) You have designed a system with split instruction and data caches. The
data cache uses writeback, and 50% of all replaced blocks are dirty. The miss rate for
instructions is 1%, and the miss rate for data is 2%. Your measurements have shown that 15% of
instructions are loads and 5% are stores, and that the average CPI (of all instructions) is 1.3
assuming no memory stalls (a "perfect" memory system). If the miss penalty for reads and writes
to main memory is 25 cycles, what is the overall CPI including memory stalls?
Problem 2. (20 points) As we have seen in class, in order to perform TLB lookup at the same
time a set-associative cache is beginning to be searched, some restrictions on the length of the
displacement field are necessary. Assume we desire to do TLB lookup concurrently with cache
search, and answer the following questions.
(a) If both the (main-memory) page size and the (cache) line size are held fixed, how does an
increase in cache size (the number of lines in the cache) affect the number of lines required in
each set (the “set size”)? Justify your answer.
(b) If the cache contains 16K words, pages are 1K words long, and lines contain 16 words, what
range of set sizes will allow simultaneous TLB and cache access?
(c) Does the required set size depend on the line size? (For example, if you redid part (b)
assuming a line size of 32 words, or 64 words, etc., would your answer change?)
(d) Suppose now that the set size and line size are held fixed. How does an increase in cache
size affect the required page size? Justify your answer.
Problem 3. (20 points) Set-associative and sectored caches are two compromises between
direct mapping and full association. A cyclic reference string of order n is a sequence of
references to blocks
0, 1, 2, … , n–2, n–1, 0, 1, 2, … , n –2, n –1, 0, 1, …
Assume that LRU replacement is used in both kinds of caches, and that
• there are f lines in each cache,
• there are b blocks per set in the set-associative cache,
• there are s sectors in the sectored cache.
• there are n distinct blocks in the cyclic reference string.
(a) Suppose b = s . Which kind of cache has a higher hit ratio? Does the answer depend on f or
n? How?
(b) Suppose b ≠ s. Is the answer still the same as in part (a)? Why?
Problem 4
.
(10 points) [Hennessy & Patterson 5.13] McFarling [1989] found that the best
memory-hierarchy performance occurred when it was possible to prevent some instructions from
entering the cache.
