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Sample Test Questions for ECE 463/
The following questions come from recent tests in CSC/ECE 506, which covers some of the same material on caches.
Question 1. (4 points for parts a–d; 2 points for parts e–f) The Tinicomputer Corporation manufacturers a machine with a cache that contains four lines. Main memory consists of 16 blocks. The cache is managed according to the LRU algorithm.
Suppose a program starts out by referencing blocks 0, 3, 4, 9, and 5, in that order. After this series of references is made, which blocks are in the cache, and what are the tags (*it is probably easiest to give the tag in binary), if the cache organization is—
(a) Direct mapping? (c) 2-way set associative?
Tag* Block number
Tag* Block number
Line Line
(b) Fully associative? (d) Sectored, with 2 sectors?
Tag* Block number
Tag* Block number
Line Line
(e) Suppose that main memory consists of 2^10 bytes. Then how large are the tag, line, and word fields for the cache of part (a)?
Tag field 2 bits Line field 2 bits Word field 6 bits
(f) Suppose that this (first-level) cache is backed by a second-level cache that is two- way set associative and contains 8 lines. Then how large are the tag, line, and word fields in the second-level cache?Hint: See pp. 395–96 of CS&G.
Tag field 2 bits Set field 2 bits Word field 6 bits
*Please give the tag values in binary or octal.
Question 2. (2 points per blank, with one exception) A computer has a main memory of size 224 (16 megabytes) and a cache of size 2^16. There are 32 bytes per cache line.
For partial credit, show your calculations!
(a) If the cache were fully associative, how large (how many bits) would the tag and word fields be?
Tag field: 19 bits Word field: 5 bits
A line size of 32 implies a word field of 5 bits. The tag field is whatever is left over, namely 19 bits.
(b) If the cache utilized direct mapping , how large would these fields be?
Tag field: 8 bits Block field: 11 bits Word field: 5 bits
The word field is again 5 bits. The size of the block field depends on the number of blocks; there are 216 ÷ 25 = 2^11 blocks, so the block field is 11 bits long. The tag field is whatever is left over, namely, 8 bits.
(c) If the cache were set associative with a set size of 4, how large would these fields be?
Tag field: 10 bits Set field: 9 bits Word field: 5 bits
As in part (b), there are 2^11 blocks in the cache. With a set size of 4, this means 2^11 ÷ 22 = 2^9 sets. Thus, the set field is 9 bits wide. The word field is 5 bits, leaving 10 bits for the tag field.
(d) If the cache were sectored with a sector size of 4 blocks, how large would these fields be? Tag field: 17 bits Sector field: 2 bits Word field: 5 bits
The sector field merely needs to identify the block within a sector, so it would be two bits wide. The tag field is therefore 24–2–5 = 17 bits.
Question 3. Consider a computer which has a set-associative cache, uses paged memory with a TLB, and whose physical memory is low-order interleaved. Which of the following characteristics are
- necessary, or important for good performance; or
- immaterial (not important)?
Explain your answers! You may assume that the number of memory modules is less than the number of words per page.
(a) The length of a cache line is a power of 2.
Answer: Important for good performance. If the cache line were not a power of 2 in length, complicated hardware would be needed to separate the physical address into set and word/byte fields. Moreover this hardware would be in the critical path for every memory reference, and would therefore slow the machine.
(b) The L2 cache contains exactly the same number of sets as the L1 cache.
Answer: Immaterial to performance. The L2 cache must containat least as many sets as the L cache, or otherwise the inclusion property will not hold. But it is not important for it to bethe same as the number of sets in the L1 cache.
(c) The page number is disjoint from the set number.
Answer: Important to good performance. If the page number is disjoint from the set number, then we can start searching the cache while we look up the page number in the TLB.
Answer: It is easy to see that fully associative is better than direct mapped, which maps all of the blocks to frame 1, or set associative, which makes all the blocks compete for set 1. In both cases, misses will occur on every reference. On the other hand, fully associative encounters only 4 misses, since all four blocks can fit in the cache simultaneously. The only remaining question is whether a sectored cache can match fully associative. The trace at the right shows that it cannot.
This should be no surprise, as all the blocks are forced to compete for the last frame of the two sectors.
Sectored
Sector 0
Sector 1
7 misses
