Procedural Blocks and Assignments in Digital Logic Design, Exercises of Digital Systems Design

Procedural blocks, their types (begin-end and fork-join), and procedural assignment statements in digital logic design. It also covers the concept of data types and their assignment in procedural blocks. Examples of procedural blocks and assignments using vhdl code.

Typology: Exercises

2011/2012

Uploaded on 07/26/2012

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P
ROCEDURAL
B
LOCKS
P
ROCEDURAL
B
LOCKS
|Behavioral Level Coding is done within
PdlBlkTh tt f
P
roce
d
ura
l
Bl
oc
k
s.
Th
ere are
t
wo
t
ypes o
f
Procedural Block.
y
begin end
y
begin
………………
end
,
,
instr.01 instr.02 #delay instr.03 instr.04
Ti Li
Ti
me
Li
ne
t=0 t=delay
P
ROCEDURAL
B
LOCKS
(C
ONT
D
)
P
ROCEDURAL
B
LOCKS
(C
ONT
D
)
|fork………………join
All i i i hi hi f bl k d
y
All
i
nstruct
i
ons w
i
t
hi
n t
hi
s type o
f
bl
oc
k
are execute
d
in a parallel manner.
#delay
,
instr.02 instr.04
,
instr.01 instr.03
Time Line
t=0 t=delay
EXAMPLE:
Wh t th fi l l f i
module iaf1;
integer i, j;
initial begin
Wh
a
t
are
th
e
fi
na
l
va
l
ues o
f
i
and j?
At t=0 i and j are assigned values 3 & 4
initial
begin
i = 3;
j = 4;
fork
At
t=0
,
i
and
j
are
assigned
values
3
&
4
respectively.
Then program enters the fork-join block. At
t
=
1, i and j are sampled and assigned new
#1 i = j;
#1 j = i;
join
t1,
i
and
j
are
sampled
and
assigned
new
,
end
endmodule module iaf1 ;
integer i, j;
iiilb i
,
How to solve this issue?
i
n
i
t
i
a
l
b
eg
i
n
i = 3;
j = 4;
fork
Intra-
Assignmen
t Delay
Using Intra-Assignment
Delays.
fork
#1 i = #1 j;
#1 j = #1 i;
join
join
end
endmodule
PROCEDURA
L
A
SSIGNMENT
|Data types reg, integer, real and time can only
be assigned a value in Procedural Blocks.
be
assigned
a
value
in
Procedural
Blocks.
These statements are called Procedural
Assignment Statements.module ianb;
integer i j;
Procedural Assignment
Statements can be classified as:
integer
i
,
j;
,
¾Blocking Procedural Assignment:
Instructions are executed in a
se
q
uential manner.
i = #1 j;
j = #1 i;
end
end
e
n
d
m
odu
l
e
,
q
¾NonBlocking Procedural
Assignment:
e d odu e
module ianb;
integer i, j;
initial begin
RHS of all these assignment
statements (Sampling) is done at
t=0. After then at the specified delay
S
i = 3;
j = 4;
begin
i < = #1 j;
j<
=
#1 i;
they are assigned to LH
S
.
j
<
#1
i;
end
end
endmodule
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B

LOCKS

P

ROCEDURAL

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d

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k

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t^

t^

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Procedural Blocks. There are two types ofProcedural Block.^ y

begin

end

y^

begin………………end

,,

instr.

instr.

#delay

instr.

instr.

Ti
Li
Time Line

t=

t=delay

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LOCKS

(C

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’D

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(C

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fork………………join

All i

i^

i hi

hi

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k^

d

y^

All

instructions within this type of block are executed in a parallel manner.

#delay

,

instr.

instr.

,

instr.

instr.

Time Line

t=

t=delay

E

XAMPLE

:^

Wh t
th
fi^
l^
l^
f i

module iaf1;integer i, j;initial begin

Wh
at are the final values of i
and j?^ ƒ^
At t=0 i and j are assigned values 3 & 4

initial

begini = 3;j = 4;fork

ƒ^
At
t=0, i and j are assigned values 3 & 4
respectively. ƒ^
Then

program enters the fork-join block. At

t=1, i and j are sampled and assigned new

#1 i = j;#1 j = i;

join

t 1,

i and j are sampled and assigned new

,

endendmodule

module iaf1 ;integer i, j;i^ i i l b

i

,

How to solve this issue?

initial begin

i = 3;j = 4;fork

Intra- Assignment Delay

Using Intra-AssignmentDelays.

fork

#1 i = #

j;

#1 j = #

i;

join

join endendmodule

P

ROCEDURAL

A

SSIGNMENT

Data types reg, integer, real and time can onlybe assigned a value in Procedural Blocks.be assigned a value in Procedural Blocks.These statements are called ProceduralAssignment Statements.

module ianb;integer i j;

-^

Procedural AssignmentStatements can be classified as:

integer

i, j;

,

¾

Blocking Procedural Assignment:

-^

Instructions are executed in asequential manner.

i = #1 j;j = #1 i;end endendmodule

,

q

¾

NonBlocking ProceduralAssignment:

e^

d^

odu e module ianb;integer i, j;initial begin

-^

RHS of all these assignmentstatements (Sampling) is done att=0. After then at the specified delay

S

i = 3;j = 4;

begini < = #1 j;j < = #1 i;

they are assigned to LHS.

j^ <

#1 i; end endendmodule

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P

ROCEDURAL

A

SSIGNMENT

(C

ONT

’^ D

,

module ianb;integer i, j;

module ianb;integer i, j;

i and j willhave ‘dx

i and j willhave value4 and 3.

,

g^

j

initial begini = 3;j = 4;

forki = j;

g^

j

initial begini = 3;j = 4;

begini <= j;

4 and 3. RHS

i^

j; j = i;end endendmodule

i <

j; j <= i;end endendmodule

Temp
LHS

D

ATA

P

ATH

E

LEMENTS

D

ATA

P

ATH

E

LEMENTS

ALU

Registers

Memory

y

We will implement all these one by one along

,

p

y

g

their interface with each other.

,

A

RITHMETIC

& L

OGICAL

U

NIT

(ALU)

A

RITHMETIC

& L

OGICAL

U

NIT

(ALU)

Adder/Subtractor Unit

Adder/Subtractor Unit

Logical Unit

Shift Unit

Shift Unit

,,

A

DDER

/S

UBTRACTOR

U

NIT

(AU)

/S

U

C O

U

(^

U)

A

B

Carry in

Add_or_Sub

AU

,

0:add1:Subtract

AU

En_AU

,

F

Carry out

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