HDL Design with Verilog: Procedural Assignments & Blocking vs Nonblocking, Slides of Data Communication Systems and Computer Networks

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• SS-CARE School of Engineering Spring 2007 HDL Based Digital Design CE
  • Lecture

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

IMPLEMENTATION 2^ module mux4_1 (in1, in2, in3, in4, s0, s1 out);^ „^ // Module 4-to-1 multiplexer using data flow modeling^ „^ // Port declarations from the I/O diagram^ output out;^ input in1, in2, in3, in4;^ input s1, s0;^ // data flow logic for 4:1 mux^ assign out =

s1? (s0? In4 : in3) : (s0? In2 : in1); endmodule

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 4-bit Full Adder with Carry Lookaheadmodule fulladd4(sum, c_out, a, b, c_in);// Inputs and outputsoutput [3:0] sum;output c_out;input [3:0] a,b;input c_in;// Internal wireswire p0,g0, p1,g1, p2,g2, p3,g3;wire c4, c3, c2, c1;// compute the p for each stageassign p0 = a[0] ^ b[0], p1 = a[1] ^ b[1], p2 = a[2] ^ b[2], p3 = a[3] ^ b[3];// compute the g for each stageassign g0 = a[0] & b[0], g1 = a[1] & b[1], g2 = a[2] & b[2], g3 = a[3] & b[3];// compute the carry for each stage// Note that c_in is equivalent c0 in the arithmetic equation for// carry lookahead computationassign c1 = g0 | (p0 & c_in), c2 = g1 | (p1 & g0) | (p1 & p0 & c_in),c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & c_in),c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) | (p3 & p2 & p1 & p0 & c_in);// Compute Sumassign sum[0] = p0 ^ c_in, sum[1] = p1 ^ c1, sum[2] = p2 ^ c2, sum[3] = p3 ^ c3;// Assign carry outputassign c_out = c4;endmodule

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Behavioral Modeling^ Behavioral Modeling

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Behavioral Modeling!^ „^ HLL constr^ „^ (while, if –else, case)^ Procedural blocks

(always, initial)^ Register^ Transfer Level

(RTL)

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Procedural Blocks

Procedural^ Blocks „^ There are two structured procedurestatements in Verilog: always andinitial

initial Block^

always^ Block

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Initial and Always^ „^ Multiple statements perblock^ „^ Proceduralassignments^ „^ Timing control^ „^ control^ „^ Initial blocks executeonce^ „^ at t = 0^ „^ Always blocks executecontinuously^ „^ at t = 0 and repeatedlythereafter

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

initial Block „^ All statements inside an initial statement constitutean initial block. „^ An initial block starts at time 0, executes exactlyonce during a simulation, and then does notexecute again. „^ If there are multiple initial blocks, each block startsto execute concurrently at time 0. „^ Each block finishes execution independently ofother blocks. „^ Multiple behavioral statements must be grouped,typically using the keywords begin and end.

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

initial Block^ „^ This block starts with initial keyword^ „^ This is non synthesizable^ „^ Non RTL^ „^ This^ block is used only in stimulus^ „^ All initial blocks execute concurrently inarbitrary order^ „^ They execute until they come to a #delayoperator^ „^ Then they suspend, putting themselves in theevent list delay time units in the future^ „^ At delay units, they resume executing wherethey left off

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

initial Block

module stimulus; reg x,y, a, b, c; initial begin^ c=1’b0;^ #5^ a=1’b1;^ #25 b=1’b0; end initial begin^ #10 x=1’b0;^ #25 y=1’b1; end initial^ #50 $finish; endmodule

initial Block starts at time 0,executes only once during asimulation Multiple statements must be groupedusing the keywords begin and end.Incase^ of^ a^

single^ behavioral statement, grouping is not necessary.

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

always Block „^ This block starts with always keyword „^ This block is like H/W „^ The always block can be viewed as continuouslyrepeated activity in a digital circuit starting frompower on

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

always Block „^ All behavioral statements inside an alwaysstatement constitute an always block. „^ The always statement starts at time 0 andexecutes the statements in the always blockcontinuously in a looping fashion. „^ This statement is used to model a block ofactivity that is repeated continuously in adigital circuit.

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Example

module clock_gen; reg clk; initial^ clk = 1’b0; always @ (clk)^ #10 clk = ~clk; initial^ #1000 $finish; endmodule always Block starts at time 0. Clock is initialized inside a separateinitial^ statement.^

If^ we^ initialize^ the clock inside the always block, clockwill^ be^ initialized

every^ time^ the always block is entered.

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Procedural assignments^ „^ Procedural assignments update values ofreg, integer, real, or time variables^ „^ assignment ::= variable_lvalue = [delay_or_event_control ] expression^ „^ The left-hand side of a proceduralassignment can be one of thefollowing:^ „^ A reg, integer, real, or time register variable ora memory element^ „^ A bit select of these variables (e.g., addr[0])^ „^ A part select of these variables (e.g.,addr[31:16])^ „^ A concatenation of any of the above