Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Material Type: Notes; Class: Computer Organization; Subject: Computer Science and Engineering ; University: University of Nebraska - Lincoln; Term: Unknown 1989;
Typology: Study notes
1 / 23
This page cannot be seen from the preview
Don't miss anything!
2
3
Y86 Instruction Set Byte 0 1 2 3 4 5
pushl rA A (^0) rA 8
jXX Dest (^7) fn Dest
popl rA B (^0) rA 8
call Dest (^8 0) Dest
rrmovl rA, rB (^2 0) rA rB irmovl V, rB (^3 0 8) rB V rmmovl rA, D(rB) (^4 0) rA rB D mrmovl D(rB), rA (^5 0) rA rB D OPl rA, rB (^6) fn rA rB
ret 9 0
nop 0 0 halt 1 0
addl 6 0 subl 6 1 andl 6 2 xorl 6 3
jmp 7 0 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6
4
Building Blocks
Combinational Logic
Storage Elements
Register file
A
B
W (^) dstW
srcA
valA
srcB
valB
valW
Clock
fun
A
7
SEQ Hardware
Structure
Access same memory space Data: for reading/writing program data Instruction: for reading instructions
Instruction Instructionmemorymemory incrementincrement PCPC
CCCC (^) ALUALU
memorymemoryData^ Data
Fetch
Decode
Execute
Memory
Write back
icoderA , rB , ifun valC
RegisterRegister^ A^ filefileB^ M E
Register Register^ A^ filefileB^ M E
PC
valP
srcA, srcBdstA, dstB
valA, valB
aluA, aluB
Bch
valE
Addr, Data
valM
valE, valM
newPC
8
SEQ Stages
Instruction Instructionmemorymemory incrementincrement PCPC
CCCC (^) ALUALU
memorymemoryData^ Data
Fetch
Decode
Execute
Memory
Write back
icoderA , rB , ifun valC
RegisterRegister^ A^ filefileB^ M E
Register Register^ A^ filefileB^ M E
PC
valP
srcA, srcBdstA, dstB
valA, valB
aluA, aluB
Bch
valE
Addr, Data
valM
valE, valM
newPC
9
Instruction Decoding
Instruction Format
5 0 rA rB D
10
Executing Arith./Logical Operation
OPl rA , rB 6 fn (^) rA rB
13
Stage Computation: rmmovl
rmmovl rA, D(rB) icode:ifun ←←←← M 1 [PC] rA:rB ←←←← M 1 [PC+1] valC ←←←← M 4 [PC+2] valP ←←←← PC+
Fetch
Read instruction byte Read register byte Read displacement D Compute next PC valA ←←←← R[rA] valB ←←←← R[rB] Decode Read operand A Read operand B valE ←←←← valB + valC Execute Compute effective address
Memory M 4 [valE] ←←←← valA Write value to memory Write back PC update PC ←←←← valP Update PC
14
Executing popl
popl rA b (^0) rA 8
15
Stage Computation: popl
Popped value New stack pointer
popl rA icode:ifun ←←←← M 1 [PC] rA:rB ←←←← M 1 [PC+1]
valP ←←←← PC+
Fetch
Read instruction byte Read register byte
Compute next PC valA ←←←← R[ %esp ] valB ←←←← R [ %esp ] Decode Read stack pointer Read stack pointer valE ←←←← valB + 4 Execute Increment stack pointer
Memory valM ←←←← M 4 [valA] Read from stack R[ %esp ] ←←←← valE R[rA] ←←←← valM
Write back
Update stack pointer Write back result PC update PC ←←←← valP Update PC
16
Executing Jumps
jXX Dest 7 fn Dest fall thru:^ XX^ XX
target:^ XX^ XX
19
Stage Computation: call
call Dest icode:ifun ←←←← M 1 [PC]
valC ←←←← M 4 [PC+1] valP ←←←← PC+
Fetch
Read instruction byte
Read destination address Compute return point
valB ←←←← R[ %esp ] Decode Read stack pointer valE ←←←← valB + – Execute Decrement stack pointer
Memory M 4 [valE] ←←←← valP Write return value on stack Write R[ %esp ] ←←←← valE back
Update stack pointer
PC update PC ←←←← valC Set PC to destination
20
Executing ret
ret 9 0
return:^ XX^ XX
21
Stage Computation: ret
ret icode:ifun ←←←← M 1 [PC] Fetch
Read instruction byte
valA ←←←← R[ %esp ] valB ←←←← R[ %esp ] Decode Read operand stack pointer Read operand stack pointer valE ←←←← valB + 4 Execute Increment stack pointer
Memory valM ←←←← M 4 [valA] Read return address Write R[ %esp ] ←←←← valE back
Update stack pointer
PC update PC ←←←← valM Set PC to return address
22
Computation Steps
OPl rA, rB icode:ifun ←←←← M 1 [PC] rA:rB ←←←← M 1 [PC+1]
valP ←←←← PC+
Fetch
Read instruction byte Read register byte [Read constant word] Compute next PC valA ←←←← R[rA] valB ←←←← R[rB] Decode Read operand A Read operand B valE ←←←← valB OP valA Set CC Execute Perform ALU operation Set condition code register Memory [Memory read/write] Write R[rB] ←←←← valE back
Write back ALU result [Write back memory result] PC update PC ←←←← valP Update PC
icode,ifun rA,rB valC valP valA, srcA valB, srcB valE Cond code valM dstE dstM PC
25
SEQ Hardware
E.g., memories, ALU
Describe in HCL
Instruction Instructionmemorymemory incrementincrement PCPC
CCCC ALUALU
memorymemory^ DataData
NewPC
rB
dstE dstM
ALUA ALUB
Mem.control Addr
srcA srcB
read write
ALUfun.
Fetch
Decode
Execute
Memory
Write back
data out
Register Register^ Afile^ fileB^ M E
Register Register^ Afile^ fileB^ M E
Bch
dstE dstM srcA srcB
icode ifun rA
PC
valC valP
valA valB
Data valE
valM
PC
newPC
26
Fetch Logic
Predefined Blocks
Instruction memory
Instruction memory
PC increment
PC increment
icode ifun rA rB
PC
valC valP
Need regids
Need Instr valC valid
SplitSplit Align Align Byte 0 Bytes 1-
27
Fetch Logic
Control Logic
Instruction memory
Instruction memory
PC increment
PC increment
icode ifun rA rB
PC
valC valP
Need regids
Need Instr valC valid
SplitSplit Align Align Byte 0 Bytes 1-
28
Fetch Control
Logic
pushl rA A (^0) rA 8
jXX Dest 7 fn Dest
popl rA B 0 rA 8
call Dest (^8 0) Dest
rrmovl rA, rB (^2 0) rA rB irmovl V, rB 3 0 8 rB V rmmovl rA, D(rB) (^4 0) rA rB D mrmovl D(rB), rA 5 0 rA rB D OPl rA, rB (^6) fn rA rB
ret 9 0
nop 0 0 halt 1 0
pushlpushl rArA AAA (^000) rArArA 888
jXXjXX DestDest 777 fnfnfn DestDest
poplpopl rArA BBB 000 rArArA 888
callcall DestDest (^888 000) DestDest
rrmovlrrmovl rArA,, rBrB (^222 000) rArArA rBrBrB irmovlirmovl VV,, rBrB 333 000 888 rBrBrB VV rmmovlrmmovl rArA,, DD((rBrB)) (^444 000) rArArA rBrBrB DD mrmovlmrmovl DD((rBrB),), rArA 555 000 rArArA rBrBrB DD OPlOPl rArA,, rBrB (^666) fnfnfn rArArA rBrBrB
retret 999 000
nopnop 000 000 halthalt 111 000
bool need_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL };
bool instr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL };
31
E Destination
None
R[ %esp ] ←←←← valE Update stack pointer
None
R[rB] ←←←← valE
OPl rA, rB Write-back rmmovl rA, D(rB)
popl rA
jXX Dest
call Dest
ret
Write-back
Write-back
Write-back
Write-back
Write-back
Write back result
R[ %esp ] ←←←← valE Update stack pointer
R[ %esp ] ←←←← valE Update stack pointer int dstE = [ icode in { IRRMOVL, IIRMOVL, IOPL} : rB; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't need register ];
32
Execute Logic
Implements 4 required functions Generates condition code values
Register with 3 condition code bits
Computes branch flag
CC CC ALUALU
ALU A
ALU B
ALU fun.
Bch
icode ifun valC valA valB
valE
Set CC
bcond bcond
33
ALU A Input
valE ←←←← valB + –4 Decrement stack pointer
No operation
valE ←←←← valB + 4 Increment stack pointer
valE ←←←← valB + valC Compute effective address
valE ←←←← valB OP valA Perform ALU operation
OPl rA, rB Execute rmmovl rA, D(rB)
popl rA
jXX Dest
call Dest
ret
Execute
Execute
Execute
Execute
Execute valE ←←←← valB + 4 Increment stack pointer **int aluA = [ icode in { IRRMOVL, IOPL } : valA; icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valC; icode in { ICALL, IPUSHL } : -4; icode in { IRET, IPOPL } : 4;
];**
34
ALU Operation
valE ←←←← valB + –4 Decrement stack pointer
No operation
valE ←←←← valB + 4 Increment stack pointer
valE ←←←← valB + valC Compute effective address
valE ←←←← valB OP valA Perform ALU operation
OPl rA, rB Execute
rmmovl rA, D(rB)
popl rA
jXX Dest
call Dest
ret
Execute
Execute
Execute
Execute
Execute valE ←←←← valB + 4 Increment stack pointer int alufun = [ icode == IOPL : ifun; 1 : ALUADD; ];
37
Memory Read
OPl rA, rB Memory rmmovl rA, D(rB)
popl rA
jXX Dest
call Dest
ret
No operation
Memory M 4 [valE] ←←←← valA Write value to memory
Memory valM ←←←← M 4 [valA] Read from stack
Memory M 4 [valE] ←←←← valP Write return value on stack
Memory valM ←←←← M 4 [valA] Read return address
Memory No operation
bool mem_read = icode in { IMRMOVL, IPOPL, IRET };
38
PC Update Logic
New PC
New PC
icode Bch valC valM valP
PC
39
PC
Update
OPl rA, rB
rmmovl rA, D(rB)
popl rA
jXX Dest
call Dest
ret
PC update PC ←←←← valP Update PC
PC update PC ←←←← valP Update PC
PC update PC ←←←← valP Update PC
PC update PC ←←←← Bch? valC : valP Update PC
PC update PC ←←←← valC Set PC to destination
PC update PC ←←←← valM Set PC to return address int new_pc = [ icode == ICALL : valC; icode == IJXX && Bch : valC; icode == IRET : valM; 1 : valP; ];
40
SEQ Operation
State
Combinational Logic
Combinational Logic (^) Data memory
Data memory
Register file
Register file
PC 0x00c
CC CC Read Ports Write Ports
ReadRead WriteWrite
