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MODULE 1
TOPICS COVERED:-
- Introduction to the general concept of microprocessor
- I/O subsystem , programming the system
- ALU
- Instruction execution, instruction word format
- Addressing modes
- Address/data/control bus
- Tristate bus
- Interfacing i/o device
- Data transfer scheme
- Architectural advancement of microprocessor
- Evolution of processor
INTRODUCTION
A computer basically consists of the following parts:-
- I/O devices
- Memory
- CPU
The CPU is the brain of the computer irrespective of its size. The CPU normally consists of a large scale integrationcircuit called Microprocessor and works as central processing unit of a microcomputer.
Input Devices give data or information as an input to the CPU and it processes the data or information given by the devices. Memory stores the data or information, Output Devices give the required data as output to the user.
A digital component in which one microprocessor has been provided to act as a CPU is known as Microcomputer. Desktop computer, laptop computer, palm computer, notebook are the ones which contain only one microprocessor to act as a CPU.
Microprocessor:-
Definition- A microprocessor is a multipurpose programmable, clock driven, semiconductor device consisting of electronic logic circuit manufactured by using very large scale integration (VLSI) technique.
- The Microprocessor is capable of performing various computing functions and making decisions to change the sequence of program executions.
- The microprocessor application are classified primarily into two categories:-
- Reprogrammable systems
- Embedded System
- Microprocessor can perform the following operations:-
- Read data from memory
- Write data into memory
- Accept data from input devices
- Sends data to output devices
- Data processing
- Arithmetic and logic operations
- The microprocessor can be divided into 3 basic units:- 1) Arithmetic and logic unit 2) Register Array 3) Control unit.
ARITHMETIC AND LOGIC UNIT (ALU)
- An ALU is a combinational circuit that performs arithmetic and logical operation on the data stored in accumulator.
- Results of operation by ALU are placed back in the accumulator.
- Typical operations performed by ALU includes add, shift/rotate, compare, increment, decrement, AND, OR, XOR, complement, clear, pre-set etc.
- Apart from performing these operation, ALU also contains important information about certain conditions that occur during these mathematical operation.
TWO BYTE INSTRUCTION :
In this kind of instruction, the first byte is for the opcode and the second byte is for the operand or the code associated with the memory address. such instructions are stored in two consecutive memory locations. if the instruction is two byte, then it requires two machine cycle. The first machine cycle is for opcode fetch and the second machine cycle is either for memory read/memory write i/o read or i/o write.
EX: MVI B,62; ADI 58; ORI 43; IN 89.
THREE BYTE INSTRUCTION:
In this type of instruction, the first byte is for opcode and the second and third byte is for an operand code associated with the memory address. Such instructions are stored in 3 consecutive memory locations. If the instruction is of three bytes, then it requires three machine cycles. The first machine cycle is for opcode fetch and the second and third machine cycle is either for memory read/memory write I/O read or I/O write.
EX: LDA 8062; LXI H, 8057; JMP 7809.
Instruction format
Intel 8085 handles 8 bit of data as it is an 8 bit microprocessor. It is designed to process 8 bit of data at a time. If a 16 bit data has to be stored then they are stored in consecutive memory locations.
There are various ways to specify data for an instruction:
8 bit or 16 bit data may be directly given in the instruction. E.g. ADI 07H, LXI 7051H etc. The address of the memory location or I/O devices may be given in the instruction itself. Ex LDA 8582H, IN 02H etc. In some instructions only one register is specified. Ex ADD B In some instructions we write two registers. Ex MOV D,E In some instructions the data is implicit or implied. Ex CMA, RRC, RAL.
Addressing Modes
Addressing modes are an asset of the instruction set architecture in most CPU designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identity the operand of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in register and/or constants contained within machine instruction or elsewhere.
. For 8085 there are five addressing modes. They are:
DIRECT ADDRESSING MODE
In type of addressing mode the address of the operand or the data is given to the instruction itself. This type of mode is used to accept data from outside devices to store the data in the accumulator and send the data stored in the accumulator to the output devices.
E.g. IN 02 (to accept the data from the port 02h and store the same in the accumulator)
OUT 01H (send the data from the accumulator to the output port)
LHLD address (load H-L pair direct.)
REGISTER ADDRESSING MODE
In type of addressing mode the address is provided through the registers. Here the operand is GPR.
E.g. MOV Rd,Rs (move a copy of data from the source register to the destination register)
ADD B (add the content of b to the accumulator and the value is stored in the accumulator)
INR C (Increment the value of the register c by 1)
REGISTER INDIRECT ADDRESSING MODE
In type of addressing mode the address of the operand or the data is specified by a pair of register before the execution of the instruction itself. Here the address of the memory is not directly given in the instruction. The address of the memory resides in H-L pair and this has been already specified in an earlier instruction.
E.g. LXI H, 8175; MOV B, M (move the data from memory specified by H-l pair to the register b)
LXI H, 8763; ADD M (Add the content of memory specified of the H-L pair to the accumulator)
IMMEDIATE ADDRESSING MODE
in type of addressing mode the data is directly associated in the instruction itself. It loads immediate data to the destination provided in the instruction.
E.g. MVI r. D8 (move an 8 it data directly to the register)
ADI 62H (add 62 to the accumulator content and store the result in the accumulator)
JMP address, JC address, CPI D8.
IMPLICIT ADDRESSING MODE
There are certain instruction which are operated on the content of the accumulator. These types of construction don’t require any address of the operand.
Eg. CMA (it finds the 1’s compliment of the data present in the accumulator and stores in accumulator)
TRISTATE BUS
The Tristate logic devices have 3 states i.e. 0, 1, high impedance. Apart from input line it has a third line called ENABLE. When the ENABLE line is activated the logic gate performs its designated functions. But when ENABLE is disabled, it goes into a state High I.e. gets disconnected from the rest of the circuit
E.g. diagram of not gate
In a tristate bus, there are a number of logic devices connected. Situations arise when you don’t need the outputs of all of them simultaneously. In the diagra bus, A, B and C. Sometimes we won’t need the outputs of al the 3. The output may require only one or two of them to function at a time. In those situations, the ENABLE line is used to disconnect the logic device which is not required. A Bus with this kind of feature is called a tristate bus.
tate logic devices have 3 states i.e. 0, 1, high impedance. Apart from input line it has a third line called ENABLE. When the ENABLE line is activated the logic gate performs its designated functions. But when ENABLE is disabled, it goes into a state High Impedance state. I.e. gets disconnected from the rest of the circuit
In a tristate bus, there are a number of logic devices connected. Situations arise when you don’t need the outputs of all of them simultaneously. In the diagram given above there are 3 logic devices given in a bus, A, B and C. Sometimes we won’t need the outputs of al the 3. The output may require only one or two of them to function at a time. In those situations, the ENABLE line is used to disconnect the logic device which is not required. A Bus with this kind of feature is called a tristate bus.
tate logic devices have 3 states i.e. 0, 1, high impedance. Apart from input line it has a third line called ENABLE. When the ENABLE line is activated the logic gate performs its Impedance state.
In a tristate bus, there are a number of logic devices connected. Situations arise when you don’t need m given above there are 3 logic devices given in a bus, A, B and C. Sometimes we won’t need the outputs of al the 3. The output may require only one or two of them to function at a time. In those situations, the ENABLE line is used to disconnect the logic
ENABLE
INTERFACING I/O DEVICE
There are two schemes for allocation of addresses memories and input and
a. I/O mapped I/O scheme b. Memory mapped I/O scheme
I/O mapped I/O:-
In this scheme the address assigned to memory locations can also be assigned to I/O devices. Since the same address may be assigned to a memory location or an I/O device, the signal to distinguish whether the address on the address bus is for a memory location or an I/O device.
Memory mapped I/O scheme:-
In this scheme I/O devices are treated the as a memory location and one address is assigned t certain range of address is assigned to the devices and thereafter addresses are assigned to different
INPUT OUTPUT
0 OR 1 OR HIGH IMPEDANCE
INTERFACING I/O DEVICE
There are two schemes for allocation of addresses memories and input and output devices:
Memory mapped I/O scheme
In this scheme the address assigned to memory locations can also be assigned to I/O devices. Since the same address may be assigned to a memory location or an I/O device, the microprocessor must issue a signal to distinguish whether the address on the address bus is for a memory location or an I/O device.
In this scheme I/O devices are treated the as a memory location and one address is assigned t certain range of address is assigned to the devices and thereafter addresses are assigned to different
OUTPUT
output devices:-
In this scheme the address assigned to memory locations can also be assigned to I/O devices. Since the microprocessor must issue a signal to distinguish whether the address on the address bus is for a memory location or an I/O device.
In this scheme I/O devices are treated the as a memory location and one address is assigned to it. A certain range of address is assigned to the devices and thereafter addresses are assigned to different
- Synchronous: - This type of data transfer is used when device which sends data and devices which receives data are synchronised with the same clock. Works when IO devices and the CPU works with the same speed. IN/OUT instructions are used to transfer data from IO devices to memory and vice versa. Generally used in IO mapped IO scheme, can also be used with memory mapped IO scheme with proper memory read/write instruction. Data is transferred as soon as CPU gives instruction to do so. There is no need to check if the device is ready or not.
- Asynchronous: - It means at “regular intervals”. This type of data transfer scheme is used when speed of the IO device does not match with that of CPU. There is no predictability of timing characteristics. The microprocessor always pings the other device to check whether it’s ready or not. During initiation the CPU checks whether device is ready to transfer data, before the actual transfer of data the memory keeps sending signal to IO device. This is called handshaking. The CPU sends initialising signal to device during start and after actual data transfer.
Interrupt Data transfer scheme: - The program initiates the program and then executes the main program. When IO device is ready to transfer data, the interrupt signal becomes high. The CPU completes the task at hand and then it attends to the IO device. It transfers the data to the stack and then executes a subroutine called ISS (interrupt Service Subroutine). ISS execution transfers data from IO device to memory and vice versa.
Direct memory access: - For bulk transfer to or from IO device the above mentioned techniques might prove inefficient. So DMA process is ideal for transferring huge amount of data. The IO device requests the microprocessor by sending a signal. After receiving this request signal the CPU disconnects itself from memory and IO devices by tristating address, data and control bus. The CPU sends the acknowledge signal to IO device. After this data transfer takes place, and on completion IO device withdraws DMA request. Advancement of architecture of microprocessor
- Cache memory: - To speed up execution of data, a buffer between the CPU and memory is used. It consists of high speed static ram. Execution speed is equal to microprocessor speed.
- Pipelining:- This is used to speed up execution of instruction. While the execution unit is working on instructions, the queue in a CPU fetches the next set of instructions. As soon as the working on instruction is over, the next set of instructions are fed into the execution unit. There is no time wasted in fetching instructions. This technique is called pipelining.
- Multitasking or memory management: - Due to growth in hardware complexity of computers, they were used in time sharing working environment. That means a fixed amount of time is allocated to different programmes. To achieve relocatablity segmented scheme is used.
- Virtual memory system:- In this scheme the complete program is divided into several pgs. and stored in hard disk. At same time the main memory is divided into small pages.
By this we can swap the pages between hard disk and main memory. This task is performed by the operating system. Main memory size is bigger than physical memory size which is correct.
EVOLUTION OF MICROPROCESSORS
FIRST GENERATION :
The first microprocessor is intel 4004. PMOS microprocessor introduced in he year 1971 nt the intel corporation, USA. The enhanced version of this is intel 4040. Memory addressing capacity is 1kb, clock frequency is 750 khz. No of pins is 16 and clock freq is defined as the no instruction that can be executed in one sec.
Other eg. Rockwell international’s PPS-4, TOSHIBA t3472 etc
SECOND GENERATION
The first 8 bit is microprocessor is intel 8008 introduced in the year 1972 which is a 8 bit pmosmicroprocessor .in the year 1973, intel 8080 which is an 8 bit, nmos microprocessor was in traduced which is faster and compatible to TTL than that of pmos technology. But intel 8080 requires three power supplies so in the year 1975 intel 8085 , an 8 bit nmos microprocessor was introduced which requires one power supply ie +5v dc. Memory addressing : -64 kb , clock frequency – 1mhz to 6mhz. No of pins 40.
Other eg. Rockwell international’s PPS 8, ZILOG’s z-800 etc
THIRD GENERATION
In 1975, a 16 bit microprocessor was developed which is anhmos microprocessor. Memory addressing capacity: i mb to 16 mb, clock frequency 6 to 12.5 mhz, no of pins -
Other eg. Intel 8088, 80186, 80286
Intel 80186 and 80188 are integrated microprocessors beside cpu. They contain some additional components that are PIC, DMA, PC Or timer, clock generator, peripheral chip select logic. Programmable state generator and local bus controller etc. In intel 80286 besides cpu it has integrated memory management unit, four level memory protections, it supports virtual memory and operating systems.
ARCHITECTURE OF 8086 MICROPROCESSORS:
As we see the whole block diagram is divided into two parts
- Bus interface unit.
- Execution unit
The function of both of these two units is that they perform their operation together. The BIU reads the instruction operational codes from memory and store them into the instruction registers and at the time of execution the instruction in the instruction register. Due to the fetching and execution of an instruction happen together the 8286 microprocessors is called parallel processors.
BUS INTERFACE UNIT (BIU):
- The bus interface unit contains the circuit for physical address calculation and pre decoding instruction byte queue.
- The BIU makes the system bus signal available for external interfacing of the device.
- The unit is responsible for establishing communication with external device and peripherals are including memory via the bus.
- The complete physical address from contents which is 20bits long is generated using segment and offset register.
- For a generation of physical address from contents of these two registers the content of a segment register also called as segment address is shifted left bit wise 4-times and to this result, content of an offset register also called an offset address is added to produce a 20 bit physical address.
- The bus interface unit has a separate address to perform this procedure for obtaining a physical address while addressing mode the segment address values is to be taken from an appropriate segment register depending upon the offset may be the content of IP, BX,SI,DI,SP,BP or an intermediate 16 bit values depending upon addressing mode.
- In case of 8085 once operational code is fetched and decoded the external bus remain free for same time while the processor internally executes. While the fetched instruction is executed internally, the external bus is used to fetch the machine code of the next instruction and arrange it I a queue known as “PREDECODED INSTRUCTION BYTE QUEUE”.
- The operational code is fetching by BIU and EU executes the previously decode instruction concurrently. The BIU along with the EU perform a pipe line.
- The BIU thus manages the complete interface execution unit with memory and input and output decides under the control of timing and control unit.
EXECUTION UNIT:
- The execution unit contains the register.
- It has 16 bit ALU, able to perform arithmetic and logical operations.
- The 16 bit flag register reflects the result of execution by the ALU.
- The decoding unit decodes the opcode bytes issued from the instruction byte queue.
- The execution unit may pass the result to the bus interface unit for storing them in memory.
PIN CONFIGURATION OF 8086:
- Pin configuration of 8086 microprocessors available in three clock rates, 5 MHZ,8 MHZ, MHZ.
- It is fabricated by HMOS technology and package in a 40 pin DIP (dual in package).
- It can be operated in single processors or multiple processors configuration etc.
PIN DIAGRAM OF INTEL 8086:
THERE ARE THREE CATAGORIES:
transfer takes place from an even address on (D0-D15) data bus, the function of (BHE)’ is shown in the table below.
(BHE)’ A 0 OPERATION
0 0 16 BIT TRANSFER
0 1 UPPER BYTE TRANSER
1 0 LOWER BYTE TRANSFER
1 1 NONE
(RD)’ READ PIN: -
PIN NO.- 32
Type – output
Function:
This signal indicates that up is performing a memory or input output read operation.
READY:
PIN NO.- 22
TYPE- INPUT
FUNCTION:
The microprocessors sample , the ready signal at rising edge clock during T3 clock cycle, if the signal is active high then microprocessors enter no wait states in its internal operation , otherwise its enter wait state , in its internal operation.
INTR:
PIN NO.V- 18
TYPE- INPUT
FUNCTION:
This signal is sampled during last clock of each instruction to determine whether the microprocessor should enter into an interrupt acknowledgement cycle.
(TEST)’:
PIN NO - 23
TYPE – INPUT
FUNCTION:
The signal is used in wait instruction before execution the instruction microprocessor check the (TEST)’ pin status.
If TEST =1, then microprocessor will not enter into wait state , that is - execution will continue.
If TEST = 0, then the microprocessor will enter into wait state.
NMI(NON MARKABLE INTERRUPT):
PIN- 17
TYPE: - INPUT
FUNCTION:
This signal cannot be makeable internally by software. this is a edge triggered signal which cause a type 2 interrupt when signal is active high interrupt service is vector to via an interrupt vector.
RESET:
PIN NO.- 21
TYPE- INPUT
FUNCTION:-
When this pin is high it immediate reset the microprocessor, When the pin status is high immediately the segment count is FFFFH and so the base address at that moment is FFFF 0 H
3. REGISTER ORGANISATION:-
The INTEL 8086 contains the following register
(a) General purpose register
(b) Pointer and index register
(c) Segment register
(d) Instruction pointer
(e) Status Flags
(a) General Purpose register:-
(i) The AX, BX, CX and DX are the general purpose 16-bit register.
(ii) AX is used as 16-bit accumulator.
(iii) AX ->AH (For higher 8-bit)
AL (For lower 8-bit)
It contains sign flag, zero flag, auxiliary carry flag, Parity flag and overflow flag.
(b) Machine cycle:-
It is the higher byte of 16 bit status flag register. It contains directional flag, Trap flag, Interrupt flag etc.
(1) Carry Flag:-
The flag register is set to 1 when there is unsigned overflow. When there is no overflow this flag is set 0.
(2) Parity Flag:-
The flag is set to be 1 when there is even no. of one bits in result and it 0 when there is odd no. of one bits.
(3)Auxiliary Flag:-
Set to be 1 when there is an unsigned overflow for low nibble (4 bits).
(4)Zero Flag:-
Set to be 1 when result is zero, for non-zero results this flag is set to 0.
(5)Sign Flag:-
Set to 1 when result is negative, when result is positive it is set to 0.
(6) Trap Flag:-
It is set; the processor enters the single step execution mode or a trap interrupt generated after execution of each instruction.
(7)Direction Flag:-
This is used string manipulation instruction D=0, then the string is processed beginning from lower address to the higher address.
D=1, then the string is processed beginning higher address to the lower address.
(8)Interrupt Flag:-
This flag is set, the mask able interrupt recognized by the CPU otherwise they are ignored.
(9)Overflow Flag:-
This flag is set, if an overflow occurs i.e. if the result signed operation is large enough to accommodate in a destination register.
4. CLOCK GENERATOR INTEL 8284:-
Pin Configuration:-
X1 X2:-
Pin no : 17, Type: Input Function: Those two pins are used for external crystal connection .The required crystal frequency must be exactly three times the required frequency. So to achieve a clock frequency of 3 MHZ the crystal frequency is 9MHZ.
EF1:-
Pin no : 14 Type : Input Function: It is called alternate clock input. It supplies externally generated clock signal. The clock signal at EF1 is called fundamental frequency.
F/C’:-
Pin no. 18 Type : Input Function: It is used for clock source selection whether the 8284 clock generator retake clock source from x1, x2 or EF1.
If F/C’= 1 (High) then clock source will be taken from EF1.
If F/C’= 1(Low) then clock source will be taken from x1, x2.
CLK:-
Pin no : 8 Type : Output Function: This pin is direct connected to 8086 microprocessor.
OSC:-
Pin no : 12 Type : Output Function: OSC is an oscillator output running at crystal or EF1 frequency.
PCLK:-
