Programmable Logic Devices - Digital Logic Design - Lecture Slides, Slides of Digital Logic Design and Programming

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Lecture No. 21

Programmable Logic Devices

Recap

 PLA Device

 Implementing 0 and 1

 Implementing Odd-Prime Number

 GAL Operation

 EECMOS cells

 Programming PLDs

GAL16V

 Emulate PALs three modes

 8 inputs

 2 special function inputs

 8 outputs

 8 sum-of-product terms

 Each has 8 product terms

 OLMC

 Output control (4 options)

 Feedback control (3 options)

 OR gate output (programmed polarity)

GAL16V

 Simple Mode (3 options)

 Combinational Output (fig 1)

 Combinational o/p with feedback (fig 2)

 Dedicated Input (fig 3)

 Complex Mode (2 options)

 Combinational o/p (fig 4)

 Combinational Input/output (fig 5)

 Registered Mode

ABEL

 Programming by Truth Table

 XOR gate (fig 10)

 Comparator (fig 11)

 Comparator using sets (fig 12)

 Test Vectors

 Comparator (fig 13 14)

 ABEL Input File three sections

 Declarations (device, pin, set) (fig 15)

 Logic Description

 Test Vectors

Implementing Quad MUX

 Quad 1-of-4 function table (tab 4)

 ABEL Input file for the MUX (fig 16)

 ABEL Implementation for MUX (fig 17)