Programmable Logic Devices - Intro to Digital Circuit Design - Lecture Slides, Slides of Digital Systems Design

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Programmable Logic Devices

Lecture Overview

• Programmable Logic Devices
  • Combinational PLDs
  • PLDs incorporating F/F
• Field Programmable Gate Array (FPGA)

PALs

• A PAL is like a PLA but has a fixed OR array.
• “PAL” is a register trademark of AMD

PAL Details

• PAL16L8 basic specifications
  • 16 inputs
  • 8 outputs
  • 64 AND gates each with 32 inputs
  • 8 AND gates associated with each output pin 1 of which can is used for output enable
  • Each sum of products limited to 7 product terms

Programming

• PLD Programming
  • 1. Raise programming pin to predetermined high voltage (such as 14V) to place the device in programming mode.
  • 1. Select a group of 8 fuses by applying binary address to detailed inputs.
  • 1. Apply 8 bit value to specified outputs for those fuses
  • 1. Raise a 2nd^ programming pin to the programming voltage fro programming time (ex 100 usec)
  • 1. Lower the programming pins to low voltage (0 V) to read out and verify programming
  • 1. Repeat to all fuses programmed.

Programmable Logic array

• Consists of an AND plane and an OR plane

PLA features

• AND Plane
  • Any inputs can be connected to the input of the AND gates.
  • AND gates form the product terms of the desired logic
• OR Plane
  • Perform the OR function on the product terms to form the sum of products for each logic equation for output
• Device Specification

  • inputs (n) # outputs (m) # product-terms(p)

FPGA

• Field Programmable Gate Array
  • A kind of CPLD turned inside out
  • Consists of a large # of small programmable blocks
• Manufactures
  • XILINX
  • ALTERS
  • Lattice

Sizes of FPGAs

The CLB

• 2 F/F and up to 25 to 30 gate equivalents

FPGA I/O

• The I/O of an FPGA

Interconnect - general