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Project 1 Report on Advanced Computer Architecture | ECE 587, Study Guides, Projects, Research of Computer Architecture and Organization

Portland State University (PSU)Computer Architecture and Organization

Material Type: Project; Class: ADV COMPUTER ARCH I; Subject: Elect and Computer Engineering; University: Portland State University; Term: Unknown 1989;

Typology: Study Guides, Projects, Research

Pre 2010

Uploaded on 08/16/2009

koofers-user-yig-1 🇺🇸

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Portland State University 1

Project 1



Implement a trace cache in 16-wide superscalar using sim-

outorder



Evaluate the performance in terms of IPC



Evaluate hit/miss rates and utilization of the trace cache



Due: by the end of the term,



But work as quickly as you can since there will be more

projects coming

☺

Discover Study Guides, Projects, Research of Computer Architecture and Organization Portland State University (PSU)

Partial preview of the text

Download Project 1 Report on Advanced Computer Architecture | ECE 587 and more Study Guides, Projects, Research Computer Architecture and Organization in PDF only on Docsity!

Project 1

Implement a trace cache in 16-wide superscalar using sim-outorder

Evaluate the performance in terms of IPC

Evaluate hit/miss rates and utilization of the trace cache

Due: by the end of the term,

But work as quickly as you can since there will be moreprojects coming

Hints

Copy the simplescalar to your work area andcompile by typing the following commands:

cp –f –r /stash/akkary/ss.

cd ss

make clean

make

Test by running a small binary, e.g.

sim-outorder /stash/akkary/tests/bubblesort

Coding the fill buffer

Use a large fill buffer, with a tail pointer

Advance tail when an instruction is fetched, storing when you may need in thefill buffer, e.g. instruction address, branch information, etc…

Mark instructions when they are retired and clear instructions after branchmispredictions

When a trace cache block commits, e.g. 16 instructions, the block is ready towrite into the trace cache

The buffer has to be large enough to store all instructions in the pipeline until atleast one trace block is retired, e.g. 16 instructions retired for a 16-wide traceblock

Each instruction is identified in the simulator with a unique ID stored inptrace_seq variable in the pipeline and the pipeline buffers, e.g. fetch queue,RUU, etc…

So ptrace_seq is very handy for identifying which instructions in the fill bufferare committed and which instructions are flushed due to a branch misprediction

Project 1 Report on Advanced Computer Architecture | ECE 587, Study Guides, Projects, Research of Computer Architecture and Organization

Related documents

Partial preview of the text

Download Project 1 Report on Advanced Computer Architecture | ECE 587 and more Study Guides, Projects, Research Computer Architecture and Organization in PDF only on Docsity!

Project 1

Implement a trace cache in 16-wide superscalar using sim-outorder

Evaluate the performance in terms of IPC

Evaluate hit/miss rates and utilization of the trace cache

Due: by the end of the term,

But work as quickly as you can since there will be moreprojects coming

Hints

Copy the simplescalar to your work area andcompile by typing the following commands:

cp –f –r /stash/akkary/ss.

cd ss

make clean

make

Test by running a small binary, e.g.

sim-outorder /stash/akkary/tests/bubblesort

Coding the fill buffer

Use a large fill buffer, with a tail pointer

Advance tail when an instruction is fetched, storing when you may need in thefill buffer, e.g. instruction address, branch information, etc…

Mark instructions when they are retired and clear instructions after branchmispredictions

When a trace cache block commits, e.g. 16 instructions, the block is ready towrite into the trace cache

The buffer has to be large enough to store all instructions in the pipeline until atleast one trace block is retired, e.g. 16 instructions retired for a 16-wide traceblock

Each instruction is identified in the simulator with a unique ID stored inptrace_seq variable in the pipeline and the pipeline buffers, e.g. fetch queue,RUU, etc…

So ptrace_seq is very handy for identifying which instructions in the fill bufferare committed and which instructions are flushed due to a branch misprediction

Handling branch recovery

See ruu_recover()

Fill buffer can be recovered by calling afill_recover() function from ruu_recover(), passingthe mispredicted branch ptrace_seq

Implementing timing

On every instruction fetch, check the trace cachefor a hit

If hit, update sim_cycle for LRU

If miss, delay writing the instruction in fetch queueby a fixed delay

Implement a knob to set this delay from thecommand line

Delay models the additional time needed to decodeinstructions fetched from a conventional cache