Cork Institute of Technology
Bachelor of Engineering (Honours) in Electronic Engineering -Stage 3
Bachelor of Engineering in Electronic Engineering -Stage 3
(NFQ – Level 8)
Autumn 2005
Computer Systems
(Time: 3 Hours)
Read instructions carefully
Section A: Answer any TWO questions
Section B: Answer any TWO questions
Use separate answer books for Sections A and B
All questions carry equal marks
Examiners: Prof. C. Burkley
Mr. John G. Ryan
Dr. D. Pesch
Mr. F. O’Reilly
Section A
1. (a) What is the Semantic Gap problem and how does the RISC architecture address it?
[6 marks]
(b) Explain your understanding of Exception/Interrupt handling as it applies to the
68000. In particular explain: Masking, Exception Vector Table, Handling Routines
and how Exceptions/Interrupts are identified and Handing Routines selected.
[10 marks]
(c) If you have three peripherals which you wish to connect to a 68000 and each
peripheral has only one output line for signaling an interrupt, suggest a way using
diagrams, how to connect these peripherals to the 68000 to signal interrupts and
signal the priority levels for each peripheral. [9 marks]
2. (a) Derive the following expression for the maximum percentage clock skew that can
occur on an asynchronous serial link, where N is the Serial Data Unit Size and T is
the sample period. For a 7 data bit 1 stop bit no parity determine the maximum
percentage clock skew allowable.
dt < 100
T (2N+1) [9 marks]
(b) Explain briefly what the 6850 ACIA and 68681 DUART are and what their features
are for computer communications. Using RS-232, how would you connect two
computers together with no handshaking if both computers are acting as DTEs?
[8 marks]
