ECE 6120 – Digital Design Using HDLs
Exam 2a – Spring 2007
NOTES: Closed book, except for one Verilog summary sheet and one sheet of
handwritten notes that are allowed. Please draw and write NEATLY (If I cannot read it, I
must mark it WRONG). Do all work in pencil and put all answers on YOUR paper, not
these sheets, following the specified class format (one side usage of green engineering
paper). Start each problem on a new sheet of paper. Clearly label all answers with the
problem number. Follow the 6120 HDL Guidelines for code writing style. Assume zero
delays unless otherwise specified. All code written must be synthesizable with
Quartus.
1. [15 pts] For each of the following Verilog code fragments occurring within modules,
determine whether it is synthesizable in Quartus. Answer “yes” if it is synthesizable; if
not synthesizable, answer “no” and explain why. Assume all single-letter symbols are
multibit variables, not constants. Assume that the rest of the code in each module is
properly written.
a. assign r = & (a | b);
b. always @ (a or b)
begin
r <= a + b;
if (b < 5) y <= a – 2;
else r <= a – b;
end
c. assign r = a >> b;
d. always @ (negedge clock)
begin
r = a - b;
if (a == b) r = 2’bxx;
end
e. always @ (a or b)
if (a == 3’b10x) y = a;
else y = b;
f. assign r = (b / 8) + a;
g. always @ (posedge clk)
begin
r <= b & c;
@ (posedge clk) y <= a;
end
