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An implementation of a traffic light controller using verilog hdl at the university of illinois at urbana-champaign. The design includes a system description, diagram, and verilog code for the controller module, its inputs/outputs, internal variables, initializations, and single assignment rule. The document also covers the working of the north, south, and east traffic, as well as the safety and liveness properties.
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Naresh Shanbhag, University of Illinois at Urbana-Champaign 37^37
Naresh Shanbhag, University of Illinois at Urbana-Champaign 38^38
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Naresh Shanbhag, University of Illinois at Urbana-Champaign 40^40
module main(N_s, S_s, E_s, N_g, S_g, E_g){ input N_s, S_s, E_s : boolean; output N_g, S_g, E_g : boolean; …
Naresh Shanbhag, University of Illinois at Urbana-Champaign 43^43
N_g, E_g, S_g, N_r, E_r, S_r -All green lights are initially 0 NS_lock -Initially 0. Use the init command
Naresh Shanbhag, University of Illinois at Urbana-Champaign 44^44
Naresh Shanbhag, University of Illinois at Urbana-Champaign 45^45
default{ if (N_s) next(N_r) := 1; if (S_s) next(S_r) := 1; if (E_s) next(E_r) := 1 } in default case { … (in next slide)
Naresh Shanbhag, University of Illinois at Urbana-Champaign 46^46
Naresh Shanbhag, University of Illinois at Urbana-Champaign 49^49
Naresh Shanbhag, University of Illinois at Urbana-Champaign 50^50
in case{ E_r & ~NS_lock & ~E_g : next(E_g) := 1; E_g & ~E_s : { next(E_g) := 0; next(E_r) := 0; } }
Naresh Shanbhag, University of Illinois at Urbana-Champaign 51^51
safety: assert G ~(E_g & (N_g | S_g)); N_live: assert G (N_s -> F N_g); S_live: assert G (S_s -> F S_g); E_live: assert G (E_s -> F E_g);
N_live is interpreted as AG (N_s -> AF N_g)
The liveness properties can only hold if drivers do not wait forever at a green light (FAIRNESS) -Otherwise the sensors will remain set. -Similar to the idea of disallowing continuous traffic at one light
Naresh Shanbhag, University of Illinois at Urbana-Champaign 52^52
Assume infinite occurrences of states with no pending requests N_fair: assert G F ~(N_s & N_g); S_fair: assert G F ~(S_s & S_g); E_fair: assert G F ~(E_s & E_g);
In the controller implementation these fairness constraints will have to be ensured.
Naresh Shanbhag, University of Illinois at Urbana-Champaign 55^55
Naresh Shanbhag, University of Illinois at Urbana-Champaign 56^56