SUN UltraSPARC-III Architecture: Major Units and Pipeline, Slides of Computer Architecture and Organization

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SUN ULTRASPARC-III

ARCHITECTURE

Introduction

• SPARC stands for a S calable P rocessor ARC hitecture.
• It is an open processor architecture.(i.e. Member companies to the SPARC community can freely produce the processor)
• SUN ULTRA SPARCv9 is a robust RISC architecture with

-64 bit integer address and data -Superscalar implementations -Extremely fast trap handling and context switching.

The presentation will look in detail to the SUN Microsystem’s Ultra SPARC III v9 architecture.

Communication paths between architectural units

Instruction issue unit

• This unit feeds the execution pipelines with the instructions.
• It independently predicts the control flow through a program and fetches the predicted path from the memory system.
• Fetched instructions are staged in a queue before forwarding to the two execution units: ‘ integer and floating point ’

This unit includes:

• 32-Kbyte, four-way associative ‘ Instruction cache ’
• ‘ The instruction address translation buffer ’
• A 16 K-entry ‘ branch predictor ’

Pipeline

Pipeline blocks

Stage Function

A Generate instruction fetch addresses, generate pre- decoded instruction bits on P Fetch first cycle of instructions from cache; access first cycle of branch prediction F Fetch second cycle of instructions from cache; access second cycle of branch prediction; translate virtual-to- physical address B Calculate branch target addresses; decode first cycle of instructions I Decode second cycle of instructions;enqueue instructions into the queue J Steer instructions to execution units R Read integer register file operands; check operand dependencies E Execute integers for arithmetic, logical, and shift instructions; read, and check dependency of, first cycle of data cache access floating-point register file

Pipeline

• The instruction issue unit :Stages A-J
• The execution unit :Stages R-D
• data cache: E, C, M, and W stages of the pipe in parallel with integer execution unit stages
• Floating point unit: Side pipeline parallel E through D stages of the integer pipeline

Pipeline

Instruction issue unit:

Stage A: Address lines enter to the instruction cache. All fetch address generation and selection occurs.

Stage P,F: Instruction cache access. Branch prediction Instruction address translation access

By the time the instructions are available from the cache in the B stage, we also have the physical address from the translator and a prediction for any branch that was fetched.

The processor uses all this information in the B stage to determine whether to follow a sequential or taken-branch path

Instruction buffer (queue)

• There are 2 instruction queue’s designed (instruction queue and miss queue)
• The 20-entry instruction queue decouples the fetch unit from the execution units, allowing each to proceed at its own rate
• If a branch is taken at the two cycles that should pass for filling the queue with right instructions , immediately instructions in the miss queue can be used.

Integer execute unit

• Execution pipelines can support concurrent launch up to six instructions; which can consist of: -two integer operations,A0/A1 pipelines -two FP operations, FP pipelines -one memory operation (load/store), MS pipeline -one special purpose memory operation ( prefetch cache load only) -one control transfer instruction (CTI), BR pipeline

However only four Instructions per cycle (IPC) can be executed in a sustain manner.

Register windows

WARF

• WRF consist of 32 – 64-bit registers (each of with 3 write,7 read ports and 32*64=2048 minus 64 =1984 bit write port to transport data from Architectural register file
• ARF has 160 entries (Total 8 register windows)

8x8=64 for local registers in the window 8x8=64 registers for 16 IN/OUT shared registers. 28 register for 4 set of 8 global registers.

• The WRF manages as single window & updated as results computed