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Prof. Bhairav Gupta delivered this lecture at Ankit Institute of Technology and Science for Parallel Processing course. It includes: Parallelism, Processor, Memory, System, Performance, , Latency, Prefetch, Bandwidth, Datapath, Bottlenecks
Typology: Slides
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Implicit Parallelism: Trends inMicroprocessor Architectures
Microprocessor clock speeds have posted impressivegains over the past two decades (two to three ordersof magnitude).
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Higher levels of device integration have madeavailable a large number of transistors.
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The question of how best to utilize these resources isan important one.
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Current processors use these resources in multiplefunctional units and execute multiple instructions inthe same cycle.
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The precise manner in which these instructions areselected and executed provides impressive diversityin architectures.
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SuperPipeline
Pipelining, however, has several limitations.
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The speed of a pipeline is eventually limited by thenumber of stages & time of slowest stage.
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For this reason, conventional processors rely on verydeep pipelines or super-pipeline (20 stage pipelinesin state-of-the-art Pentium processors).
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However, a typical pipeline has resource constraint,data dependency & Branch prediction issues. Approxevery 5-6th instruction is a conditional jump! Thisrequires very accurate branch prediction.
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The penalty of a prediction error grows with the depthof the pipeline, since a larger number of instructionswill have to be flushed.
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Superscalar Execution
Example…
con’d
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Scheduling of instructions is determined by a numberof factors:– True Data Dependency: The result of one
operation is an input to the next.
the same resource.
across conditional branch statements cannot bedone deterministically a-priori.
number of instructions in an instruction queue andselects appropriate number of instructions toexecute concurrently based on these factors.
constraint on superscalar processors.
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Superscalar Execution: Efficiency Considerations
Not all functional units can be kept busy at all times.
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If during a cycle, no functional units are utilized, thisis referred to as vertical waste.
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If during a cycle, only some of the functional units areutilized, this is referred to as horizontal waste.
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Due to limited parallelism in typical instruction traces,dependencies, or the inability of the scheduler toextract parallelism, the performance of superscalarprocessors is eventually limited.
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Conventional microprocessors typically support four-way superscalar execution.
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Very Long Instruction Word (VLIW)
Processors
The hardware cost and complexity of the superscalarscheduler is a major consideration in processordesign.
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To address this issues, VLIW processors rely oncompile time analysis to identify and bundle togetherinstructions that can be executed concurrently.
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These instructions are packed and dispatchedtogether, and thus the name very long instructionword.
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This concept was used with some commercialsuccess in the Multiflow Trace machine (circa).
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Variants of this concept are employed in the IntelIA64 processors & TI TMS320 C6XXX DSPs.
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Very Long Instruction Word (VLIW)
Processors: Considerations
Issue hardware is simpler.
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Compiler has a bigger context from which to selectco-scheduled instructions.
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Compilers, however, do not have runtime informationsuch as cache misses. Scheduling is, therefore,inherently conservative.
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Branch and memory prediction is more difficult.
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VLIW performance is highly dependent on thecompiler. A number of techniques such as loopunrolling, speculative execution, branch predictionare critical.
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Typical VLIW processors are limited to 4-way to 8-way parallelism.
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