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MCM6264C
MOTOROLA FAST SRAM
8K x 8 Bit Fast Static RAM
The MCM6264C is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in plastic dual–in–line and plastic small–outline J–leaded packages.
- Single 5 V ± 10% Power Supply
- Fully Static — No Clock or Timing Strobes Necessary
- Fast Access Times: 12, 15, 20, 25, and 35 ns
- Equal Address and Chip Enable Access Times
- Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
- Low Power Operation: 110 – 150 mA Maximum AC
- Fully TTL Compatible — Three State Output
ROW
DECODER
MEMORY MATRIX
256 ROWS x 32 x 9 COLUMNS
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
DQ
E
W
VCC
VSS
A
DQ
G
BLOCK DIAGRAM
E
A0 A6 A10 A
A
A
A
A
A
A
A
A
Order this document by MCM6264C/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6264C
P PACKAGE
300 MIL PLASTIC
CASE 710B–
A0 – A12............ .Address Input DQ0 – DQ7.. .Data Input/Data Output W................... .Write Enable G.................. .Output Enable E1, E2................ .Chip Enable VCC.......... .Power Supply (+ 5 V) VSS...................... .Ground
PIN NAMES
J PACKAGE
300 MIL SOJ
CASE 810B–
A
A
A
A
NC
DQ
A
A
VSS
DQ
DQ
A
A
A
A
A
E
W
VCC
DQ
DQ
DQ
DQ
E
G
A
DQ
A
REV 2 5/
Motorola, Inc. 1995
MCM6264C
MOTOROLA FAST SRAM
TRUTH TABLE (X = Don’t Care)
E1 E2 G W Mode VCC Current Output Cycle
H X X X Not Selected ISB1, ISB2 High–Z — X L X X Not Selected ISB1, ISB2 High–Z — L H H H Output Disabled ICCA High–Z — L H L H Read ICCA Dout Read Cycle L H X L Write ICCA High–Z Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol Value Unit
Power Supply Voltage VCC – 0.5 to + 7.0 V
Voltage Relative to VSS for Any Pin Except VCC
Vin, Vout – 0.5 to VCC + 0.5 V
Output Current Iout ± 20 mA
Power Dissipation PD 1.0 W
Temperature Under Bias Tbias – 10 to + 85 °C
Operating Temperature TA 0 to + 70 °C
Storage Temperature — Plastic Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to +70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 — VCC + 0.3** V
Input Low Voltage VIL – 0.5* — 0.8 V
- VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns)
DC CHARACTERISTICS
Parameter Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ± 1 μA Output Leakage Current (E1 = VIH, E2 = VIL, or G = VIH, Vout = 0 to VCC) Ilkg(O) — ± 1 μA Output Low Voltage (IOL = 8.0 mA) VOL — 0.4 V
Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V
POWER SUPPLY CURRENTS
Parameter Symbol – 12 – 15 – 20 – 25 – 35 Unit AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax) ICCA 150 140 130 120 110 mA AC Standby Current (E1 = VIH or E2 = VIL, VCC = Max, f = fmax) ISB1 45 40 35 30 30 mA Standby Current (E1 ≥ VCC – 0.2 V or E2 ≤ VSS + 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V)
ISB2 20 20 20 20 20 mA
CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter Symbol Max Unit Address Input Capacitance Cin 6 pF Control Pin Input Capacitance (E1, E2, G, W) Cin 6 pF
I/O Capacitance CI/O 7 pF
This device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to these high–impedance circuits. This CMOS memory circuit has been de- signed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
MCM6264C
MOTOROLA FAST SRAM
READ CYCLE 1 (See Note 8)
Q (DATA OUT)
A (ADDRESS)
PREVIOUS DATA VALID DATA VALID
tAVAV
tAXQX
tAVQV
READ CYCLE 2 (See Note 4)
ISB
ICC
tEHQZ
tEHICCL
DATA VALID
tGHQZ
tAVAV
tELQX
tELQV E (CHIP ENABLE)
Q (DATA OUT)
A (ADDRESS)
tELICCH
tAVQV
tGLQX
tGLQV
G (OUTPUT ENABLE)
VCC
SUPPLY
CURRENT
HIGH–Z HIGH–Z
MCM6264C
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 12 — 15 — 20 — 25 — 35 — ns 4 Address Setup Time tAVWL 0 — 0 — 0 — 0 — 0 — ns
Address Valid to End of Write tAVWH 10 — 12 — 15 — 17 — 20 — ns Write Pulse Width tWLWH, tWLEH
10 — 12 — 15 — 17 — 20 — ns
Write Pulse Width, G High tWLWH, tWLEH
8 — 10 — 12 — 15 — 17 — ns 5
Data Valid to End of Write tDVWH 6 — 7 — 8 — 10 — 12 — ns Data Hold Time tWHDX 0 — 0 — 0 — 0 — 0 — ns Write Low to Output High–Z tWLQZ 0 6 0 7 0 8 0 10 0 12 ns 6, 7, 8
Write High to Output Active tWHQX 4 — 4 — 4 — 4 — 4 — ns 6, 7, 8 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — 0 — ns NOTES:
- A write occurs during the overlap of E low and W low.
- E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
- If G goes low coincident with or after W goes low, the output will remain in a high impedance state.
- All timings are referenced from the last valid address to the first transitioning address.
- If G ≥ VIH, the output will remain in a high impedance state.
- At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
- Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B.
- This parameter is sampled and not 100% tested.
WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)
DATA VALID
tAVWL tDVWH
tAVWH
tAVAV
tWHAX
tWLWH
tWHDX
tWLQZ tWHQX HIGH–Z HIGH–Z
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
tWLEH
MCM6264C
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
28 LEAD
300 MIL PDIP
CASE 710B–
MIN MAX MIN MAX
MILLIMETERS INCHES DIM A B C D E F G J K L M N
0 °
15 °
0 °
15 °
1.27 BSC 2.54 BSC
7.62 BSC
0.050 BSC 0.100 BSC
0.300 BSC
NOTES:
- DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
- CONTROLLING DIMENSION: INCH.
- DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
- DIMENSION A AND B DOES NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
28
1
15
14
-B-
-A-
K
L
M
C
E N
F
D 28 PL
G
J 28 PL
-T-
SEATING PLANE
0.25 (0.010) M^ T A S 0.25 (0.010) M^ T B S
28 LEAD
300 MIL SOJ
CASE 810B–
MIN MAX MIN MAX
MILLIMETERS INCHES DIM A B C D E F G H K L M N P R S
0 ° 10 °
1.27 BSC
0.64 BSC
0.050 BSC
0.025 BSC 0 ° 10 °
—
—
NOTES:
- DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
- DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
- CONTROLLING DIMENSION: INCH.
- DIM R TO BE DETERMINED AT DATUM -T-.
- 810B-01 AND -02 OBSOLETE, NEW STANDARD 810B-03.
28
1
15
14
L
G
M
K DETAIL Z
DETAIL Z
S RAD
F
-B-
-A-
P
R
N
-T-^ SEATING PLANE
0.25 (0.010) T B S
0.18 (0.007) M^ T A S
0.18 (0.007) S T B S
S
M
E C
D 24 PL
H BRK
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM6264C
MOTOROLA FAST SRAM
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM6264C/D
◊ CODELINE TO BE PLACED HERE
