Intro to Electrical & Computer Engineering: Sequential Circuits & Finite State Machines, Exams of Engineering

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College of Engineering

University of Massachusetts Amherst

ENGIN 112

Introduction to Electrical and

Computer Engineering

Fall 2008

Discussion A

10. Sequential Circuit Analysis

Midterm Exam 2

• Wednesday, November 12 ( Note: Tuesday class schedule)

6:30 – 8:30 PM

ELAB II Room 119 (same room as first exam)

Closed book and notes

• Will cover material from Chapters 4 and 5:

Combinational circuits: standard design (truth tables, K-maps);

algorithmic and modular design (adders, comparators, decoders,

multiplexers).

Sequential circuits: SR latches, D latches, D flip-flops; state equations,

state tables, state diagrams; sequential circuit design; state reduction.

• Practice exam and solutions are posted on course web site
• Class on Monday, Nov. 10 will be question & answer session
• My office hours before the exam:

Friday, Nov. 7, 2:30 – 3:

Wednesday, Nov. 12, 3:30 – 5:

(In Marcus 215B)

D

> CLK

D

> CLK

x y clock

A

A’

B

B’

Example: Consider a circuit that

contains two D flip-flops. Let the

input be x and the output be y.

The state is A,B.

We can represent the circuit’s

action using state equations

that tell how the next state (at

time t+1) depends on the current

state and input:

___________________________________________________________

A(t+1) = A’(t)B(t) +A(t)B’(t)

B(t+1) = x(t)

(often drop “t” and just write:

A(t+1) = A’B+B’A

B(t+1) = x )

Also have output equation:

y = x’A + xA’

• A state table is a table that shows how the current output and the

next state depend on the current input and current state.

• In our example, state table is: Current State A B Current Input x Next State A B Output y 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 0 0 1 1 1 1 1 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 0 1 0

II. Finite State Machines

• Circuits in which the state has only a finite set of possible values are

called Finite State Machines (FSMs) - our sequential circuits are

examples of FSMs.

• FSMs for which the output at a given time depends on both the current

state and the input are called Mealy-type models. Our previous

example was a Mealy-type model. One concern with a Mealy-type

model is the need to synchronize input changes with state changes -

otherwise, the output can change even while the state remains the

same (that is, in the middle of a clock cycle rather than on a clock

pulse edge), and thus not be synchronized with the state transitions.

• FSMs for which the output is a function only of the current state are

called Moore-type models. These models automatically have

outputs that are synchronized with the states.

____________________________________________________________

Example: Consider a sequential circuit having input x , output y , and state

(A,B) satisfying the state equations:

A(t+1) = (x+B)

B(t+1) = (x+A)’

y = AB

D

> CLK

D

> CLK

x y clock

A

A’

B

B’

This is an example of a

Moore-type FSM.

What are state diagram and state table for this circuit?

____________________________________________________________

Solution Steps:

(1) Assign states and draw state diagram : We first need to decide how to

represent states in our system - often there is more than one possible

way to do this. For our example, say we define states of the form:

S = { number of customers currently in line, number of customers

currently being served}. Then we have four states: S 0 = 0,0 S 1 = 0,

S 2 = 1,0 S 3 = 1,1.

Current State Next State x=0 x= Output y x=0 x= S 0 S 0 S 1 0 0 S 1 S 0 S 2 1 1 S 2 S 1 S 3 0 0 S 3 S 1 S 3 1 1

The system input x is

the number (0 or 1) of

customers that enter the

store during a service

cycle. The output y is

the number (0 or 1) of

customers currently

being served. First fill in

the state table:

Note that the output does not depend on x

Draw State Diagram:

S 0 S 1 S 2 S 3 0/ 1/ 1/ 0/ 0/ 1/ 1/ 0/

(2) Assign bits (flip-flop states) to represent states : For this example,

we can assign D flip-flop states A = number of customers in line, B =

number of customers being served. We use D flip-flops, so we have

characteristic equations A(t+1) = DA, B(t+1) = DB.

(4) Draw K-maps for next states as functions of current states and

inputs:

x

A,B

Map for A(t+1)

A(t+1) = xB + xA = DA

x Map for B(t+1)

B(t+1) = A + xB’ = DB

A,B

Clearly: y = B

(5) Design sequential circuit that generates the functions:

D

> CLK

D

> CLK

x clock

A

A’

B = y B’

___________________________________________________________

• With this reduced set of states we have the reduced state table: Current State Next State x=0 x= Output y S 0 S 0 S 1 0 S 1 S 0 T 1 T S 1 T 1
• Comparing the state diagrams for the original and reduced set of

states, we can see that by merging states we have simplified the

overall system:

T

Original (unreduced) state diagram

• S 0 S
• S 2 S
• 0/ - 1/ - 1/ - 0/ - 0/ - 1/ - 1/ - 0/ - S 0 S - 0/ - 0/ - 1/ - 1/ - 0/ - 1/