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Synchronous Sequential Circuits-Digital Logic-Lecture 27 Slides-Electrical and Computer Engineering, Slides of Digital Logic Design and Programming

University of Alabama (UA)Digital Logic Design and Programming

Synchronous Sequential Circuits, State Diagrams, State Tables, Moore Model, Mealy Model, Finite State Machines, FSM, Active Clock Edge, Reset, Present State, Next State, State Variables, Digital Logic, Lecture Slides, Dr D J Jackson, Department of Electrical and Computer Engineering, University of Alabama, United States of America.

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Dr. D. J. Jackson Lecture 27-1Electrical & Computer Engineering
ECE380 Digital Logic
Synchronous Sequential Circuits:
State Diagrams, State Tables
Dr. D. J. Jackson Lecture 27-2Electrical & Computer Engineering
Synchronous sequential circuits
• Circuits where a clock signal is used to control
operation are called synchronous sequential
circuits
– The term active clock edge refers to the clock edge that
causes a change in state (positive or negative)
• Realized using combinational logic and one or more
flip-flops
• Two models for synchronous sequential circuits
–Moore model: circuit outputs depend only on the present
state of the circuit
–Mealy model: circuit outputs depend on the present state
of the circuit and the primary inputs
• Sequential circuits are also called finite state
machines (FSM)
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Download Synchronous Sequential Circuits-Digital Logic-Lecture 27 Slides-Electrical and Computer Engineering and more Slides Digital Logic Design and Programming in PDF only on Docsity!

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 27-

ECE380 Digital Logic

Synchronous Sequential Circuits:

State Diagrams, State Tables

Synchronous sequential circuits

  • Circuits where a clock signal is used to control

operation are called synchronous sequential

circuits

  • The term active clock edge refers to the clock edge that causes a change in state (positive or negative)
  • Realized using combinational logic and one or more

flip-flops

  • Two models for synchronous sequential circuits
    • Moore model : circuit outputs depend only on the present state of the circuit
    • Mealy model : circuit outputs depend on the present state of the circuit and the primary inputs
  • Sequential circuits are also called finite state

machines ( FSM )

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 27-

Moore versus Mealy machines

w Combinational

circuit Flip-flops Combinational circuit

Q f

clock

Mealy state machine

w Combinational

circuit Flip-flops Combinational circuit

Q f

clock

Moore state machine

Basic design steps

• We will introduce techniques for sequential

circuit design via a simple example

• Design a circuit that meets the following

specifications:

  • The circuit has one input, w , and one output, z
  • All changes in the circuit occur on the positive

edge of the clock signal

  • Output z =1 if the input w was 1 during the two

immediately preceding clock cycles

• From this specification it is obvious that z

cannot depend solely of the value of w

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 27-

State diagram

• For our example, assume the starting state is

called A

• As long as w=0, the circuit should do nothing

and z=

w=0 A/z=

reset

State diagram

• When w=1, the circuit should ‘remember’ this

by transitioning to a new state ( B )

• This transition should occur at the next

positive edge of the clock signal

w=0 A/z=

reset

B/z=

w=

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 27-

State diagram

• When in state B and w=1, the circuit should

‘remember’ this by transitioning to a new

state ( C )

w=0 A/z=

reset

B/z=

w=

C/z=1 w=

Complete state diagram

w=0 A/z=

reset

B/z=

w=

C/z=

w=0 w=

w=

w=

Moore model state diagram

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 27-

State-assigned table

C

B

A

Y 2 Y 1 Y 2 Y 1

Next state

11 dd dd d

w=0 w= Output z

Present state y 2 y (^1)

Note the addition of the y 2 y 1 =11 state. Although it is

not used, it is needed for completeness.

Next-state and output maps

• K-maps are constructed from the state table

for:

  • Circuit outputs ( z in this case)
  • Inputs for the flip-flops (next-state K-maps)

• Constructing the next-state maps depends on

the type of flip-flop (D, T, JK) used for the

implementation

  • D is the most straightforward: next-state maps

are constructed directly from the state table since

  • Q(t+1)=Q+=D
  • T and JK implementations will be covered later

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 27-

State table and next-state maps

C

B

A

Y 2 Y 1 Y 2 Y 1

Next state

11 dd dd d

w=0 w= Output z

Present state y 2 y (^1)

y 2 y (^1) w

d 0

d 0

Y 1 =wy 1 ’y 2 ’

y 2 y (^1) w

d 1

d 0

Y 2 =w(y 1 +y 2 )

State table and output map

C

B

A

Y 2 Y 1 Y 2 Y 1

Next state

11 dd dd d

w=0 w= Output z

Present state y 2 y (^1)

1 d

y (^1) y (^2)

z=y 2