VHDL Sequential Design: Processes, If-Else Statements, Case Statements, and Loops, Slides of Computer Science

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Sequential Design

Sequential code

• Code written within the following

statements execute sequentially.

• Process
• Functions
• Procedures

Process (cont..)

• A Process must be installed in the main code, and

is executed every time a signal in the sensitivity list changes (or the condition related to WAIT is fulfilled).

• Syntax:

[label:] Process (sensitivity list) [variable name type [range] [:=initial value;]] Begin (sequential code) End Process [label];

If statement

If condition then

assignments; elsif condition then assignments; ………………….. ………

else assignments;

end if;

Case (cont.)

• The case statement is very similar to when

statement.

• All the permutation must be tested, so the

keyword OTHERS may be used.

• NULL may be used, when no action is

required to take place.

e.g. When OTHERS => NULL;

entity MUX is port (A, B, C, D: in BIT; CTRL: in BIT_VECTOR(0 to 1); Z: out BIT); end MUX; architecture MUX_BEHAVIOR of MUX is constant MUX_DELAY: TIME := 10 ns; begin PMUX: process (A, B, C, D, CTRL) variable TEMP: BIT; begin case CTRL is when "00" => TEMP := A: when "01" => TEMP := B; when "10" = > TEMP := C; when "11" => TEMP := D; end case ; Z <= TEMP after MUX_DELAY; end process PMUX; end MUX_BEHAVIOR;

Example of For/loop

FACTORIAL := 1;

for NUMBER in 2 to N loop

FACTORIAL := FACTORIAL * NUMBER;

end loop;

NOTE: Range must be static.

Loop (cont.)

• WHILE/LOOP : The loop is repeated

until a condition no longer holds.

[label:] WHILE condition LOOP

(sequential statements); end LOOP [label];

Other statements

• EXIT
  • Used for ending the loop [label:] EXIT [label] [WHEN condition]
• NEXT
  • Used for skipping loop steps. [label:] NEXT [loop_label] [WHEN condition]

Example (exit and Next)

SUM := 1; J := 0;

L3: loop

J:=J+21;

SUM := SUM* 10;

if (SUM > 100) then

exit L3; -- "exit;" also would have been sufficient.

end if;

end loop L3;