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Sequential Logic Circuits
- Unlike combinational logic circuits, the output of sequential
logic circuits not only depends on current inputs but also on the
past sequence of inputs.
- Sequential circuits are constructed using combinational logic
and a number of memory elements with some or all of the
memory outputs fed back into the combinational logic forming
a feedback path or loop.
- A very simple sequential circuit with no inputs created using
inverters to form a feedback loop:
Q
QN
When this circuit is powered up it randomly outputs Q = 0 or Q =
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Sequential Logic Circuits
Combinational logic
Memory elements
Combinational outputs Memory outputs
Inputs
Sequential circuit = Combinational logic + Memory Elements
Current State of A sequential Circuit: Value stored in memory
elements (value of state variables).
State transition: A change in the stored values in memory elements
thus changing the sequential circuit from one state to another state.
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The State of A sequential Circuit The State of A sequential Circuit
- A state variable in a sequential circuit represents the
single-bit variable Q stored in a memory element in circuit.
- Each memory element may be in state 0 or state 1 depending on
the current value stored in the memory element.
- The State of A sequential Circuit:
- The collection of all state variables (memory element stored values) that at any time contain all the information about the past necessary to account for the circuit’s future behavior.
- A sequential circuit that contains n memory elements could be in one of a maximum of 2n^ states at any given time depending on the stored values in the memory elements.
- Sequential Circuit State transition: A change in the stored values in memory elements thus changing the sequential circuit from one state to another.
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Clock Signals & Synchronous Sequential CircuitsClock Signals & Synchronous Sequential Circuits
- A clock signal is a periodic square wave that indefinitely switches
values from 0 to 1 and 1 to 0 at fixed intervals.
- Clock cycle time or clock period: The time interval between two
consecutive rising or falling edges of the clock.
- Clock Frequency = 1 / clock cycle time (measured in cycles per second or Hz)
- Example: Clock cycle time = 1ms clock frequency = 1000Hz
- Synchronous Sequential Circuits: Sequential circuits that have a clock
signal as one of its inputs:
- –^ All state transitions in such circuits occur only when the clock value isAll state transitions in such circuits occur only when the clock value is either 0 or 1 or happen at the rising or falling edges of the clock dependingeither 0 or 1 or happen at the rising or falling edges of the clock depending on the type of memory elements used in the circuit.on the type of memory elements used in the circuit.
Rising edges of the clock
Falling edges of the clock
Clock signal
Clock Cycle Time
1
0
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- Latches:
- S-R Latch
- S-R Latch With Enable
- D-Latch
- Flip-Flops:
- Edge-Triggered D Flip-Flop
- Master/Slave S-R Flip-Flop
- Master/Slave J-K Flip-Flop
- Edge-Triggered J-K Flip-Flop
- T Flip-Flop With Enable
Sequential Circuit Memory Elements: Latches, Flip-Flops
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S-R Latch
• An S-R (set-reset) latch can be built using two NOR-
gates forming a feedback loop.
• The output of the S-R latch depends on current as well as
previous inputs or state, and its state (value stored) can
change as soon as its inputs change.
R
S
Q
QN
S R Q QN
0 0 last Q Last QN 0 1 0 1 1 0 1 0 1 1 0 0
Function Table
Circuit
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D-Latch
• Similar to S-R latch with an enable line, but both S, R
are generated from one input D (data) and an inverter.
• Stores the value of its input D when enable C =1.
C D Q QN
0 x Last Q Last QN
Q
QN
D
C Q Q
D C
Function Table
Circuit
Logic Symbol
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Edge-Triggered D Flip-Flop
- Uses a pair of D latches and inverters.
- Similar in behavior to a D latch except that output and state changes
happen at the rising or falling edge of an input clock.
- A D Flip-Flop triggered on the rising edge of the clock is given by:
Q Q
D CLK
D CLK Q QN
x 0 Last Q Last QN
x x Last Q Last QN
Clock
Q Q
D C
Q Q
D C
CLK
D
QM
Master Latch Slave Latch
Q QN
Circuit
Logic Symbol Function Table
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Master/Slave J-K Flip-Flop
• Solves the problem in the problem when both S=R=
• When J=K=1 the last state is inverted.
J K C Q QN
x x 0 last Q last QN 0 0 last Q last QN 0 1 0 1 1 0 1 0 1 1 last QN last Q
Q Q
S C R
Logic Symbol
Function Table
CLK
Q Q
S C
Q Q
S J C
QM
Master Latch Slave Latch Q QN K R^ R
Circuit
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Edge Triggered J-K Flip-Flop
• Created from an edge-triggered D flip-flop
Q Q
j CLK k
J K C Q QN
x x 0 last Q last QN x x 1 last Q last QN 0 0 last Q last QN 0 1 0 1 1 0 1 0 1 1 last QN last Q
Function Table Logic Symbol
Q Q
D CLK
Q
QN
J
K
CLK
Circuit
