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Understanding Sequential Circuits: Combinational vs. Sequential Logic and Flip-Flops, Study notes of Computer Numerical Control

Indian Institute of Information Technology (IIIT)Computer Numerical Control

An introduction to sequential circuits, explaining the difference between combinational and sequential logic, and discussing various types of latches and flip-flops. It also covers the race around condition and its prevention through master-slave flip-flops. Truth tables and logic symbols for different types of flip-flops and their conversions.

Typology: Study notes

2010/2011

Uploaded on 09/03/2011

krithika
krithika 🇮🇳

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bg1
Sequential circuits
•Combinational circuit – The outputs at a given instant of time depend only
on the values of the inputs at that same moment. Such a system has no
memory.
•Sequential circuit – The outputs not only depends on the current input but
also on the past history of inputs. It has memory.
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe

Partial preview of the text

Download Understanding Sequential Circuits: Combinational vs. Sequential Logic and Flip-Flops and more Study notes Computer Numerical Control in PDF only on Docsity!

Sequential circuits

  • (^) Combinational circuit – The outputs at a given instant of time depend only

on the values of the inputs at that same moment. Such a system has no

memory.

  • (^) Sequential circuit – The outputs not only depends on the current input but

also on the past history of inputs. It has memory.

Bi-stable latch

1-bit memory latch

The latch provided with

means for entering

data into the cell

Q’

Q

Q’

Q

S

R

Truth table S-R Flip-flop

S

n

R

n

Q

n+

Q

n+

’ 0 0 Q

n

Q

n

‘ 1 0 1 0 0 1 0 1 1 1??

J-K Flip-flop

Clear (Cr)

Q

Q’

J

K

Ck

Preset (Pr)

Race around condition

With IC components the propagation delay through the NAND gates is very

small, usually much less than the clock pulse width. Hence the output

oscillate back and forth between 0 and 1. This situation is called the race

around condition.

It does not occur when

tp < ∆t < T

Where tp is the clock pulse width

∆t is the propagation delay through the NAND gates

T is the clock time

Master-Slave J-K Flip-flop

Master

Slave

J

Ck

K

Pr

Cr

Q

Q’

Truth table of D Flip-flop

D

n

Q

n+

1 1 0 0 J K (^) Q’ Ck Pr Cr D Q Q’ Ck Pr Cr Q

Conversion of a
J-K Flip flop into
a D – type flip-
flop with data
input D
The logic symbol
for D – type flip-
flop

D Clock

T Flip-flop

Master

Slave

T

Ck

Pr

Cr

Q

Q’

5 – bit register

Presets Pr 4 Q^4 Pr 3 Q 3 Pr 2 Q 2 Pr 1 Q 1 Pr 0 Q 0 Preset enable Serial input Clear Clock (MSB) (LSB) S 4 R 4 Q 4 Q’ 4 Ck Pr Cr FF S 3 R 3 Q 3 Q’ 3 Ck Cr FF S 2 R 2 Q 2 Q’ 2 Ck Cr FF S 1 R 1 Q 1 Q’ 1 Ck Pr Cr FF S 0 R 0 Q 0 Q’ 0 Ck Cr FF Pr Pr Pr

Thank you