Sequential Values - Computer Engineering - Exam, Exams of Computer Science

Main points of this exam paper are: Sequential Values, Representations and Arithmetic, Most Negative Value, Bit Representations, Difference Between Sequential Values, Signed Representations, Most Positive Value, Most Negative Value, Representation, Signed Integer

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2012/2013

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ECE 2030B 1:00pm Computer Engineering Fall 2004
4 problems, 5 pages Exam Two 15 October 2004
1
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have
a question, raise your hand and I will come to you. Please work the exam in pencil and do not
separate the pages of the exam. For maximum credit, show your work.
Good Luck!
Your Name (please print) ________________________________________________
1 2 3 4 total
27 30 27 16 100
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4 problems, 5 pages Exam Two 15 October 2004

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck!

Your Name ( please print ) ________________________________________________

1 2 3 4 total

4 problems, 5 pages Exam Two 15 October 2004

Problem 1 (2 parts, 27 points) Representations and Arithmetic

Part A (15 points) For the 28 bit representations below, determine the most negative value, most positive value, and step size (difference between sequential values). All answers should be expressed in decimal notation. Fractions (e.g., 3/16ths) may be used. All signed representations are two’s complement.

representation most negative value most positive value step size

signed integer (28 bits). (0 bits) unsigned fixed-point (14 bits). (14 bits) unsigned fixed-point (19 bits). (9 bits) signed fixed-point (19 bits). (9 bits)

Part B (12 points) For each problem below, compute the operations using the rules of arithmetic, and indicate whether an overflow occurs assuming all numbers are expressed using a six bit unsigned fixed point representation and a six bit two’s complement fixed-point representation.

result

unsigned error? signed error?

4 problems, 5 pages Exam Two 15 October 2004

Problem 3 (3 parts, 27 points) Well Stated

Part A (9 points) Implement a transparent latch using that requires only ten transistors. Use gate icons rather than transistors to express your design. Label the inputs In and En , and output Out.

Part B (9 points) Implement a register with read and write enable using transparent latches, pass gates, and inverters. Use an icon for the transparent latches. Label the inputs In , WE, RE, Φ 1 , Φ 2 and the output Out.

Part C (9 points) Assume the following signals are applied to your register. Draw the output signal Out. Draw a vertical line where In is sampled. Assume Out starts at zero.

WE

In

Out

4 problems, 5 pages Exam Two 15 October 2004

Problem 4 (2 part, 16 points) Arithmetic Unit

Part A (8 points) The adder below adds two four bit numbers A and B and produces a four bit result S. Add extra digital logic to support subtraction as well as addition. Label inputs X 3 , X 2 ,

X 1 , X 0 , Y 3 , Y 2 , Y 1 , Y 0 , ADD / SUB and outputs Z 3 , Z 2 , Z 1 , Z 0.

Part B (8 points) Now define the behavior for a two’s compliment overflow detection unit.

Assume the inputs are X 3 , Y 3 , Z 3 , and ADD / SUB. The output Error is 1 for overflow.

ADD / SUB = 0 ADD / SUB = 1

X 3 Y 3 Z 3 Error X 3 Y 3 Z 3 Error

0 0 0 0 0 0

1 0 0 1 0 0

0 1 0 0 1 0

1 1 0 1 1 0

0 0 1 0 0 1

1 0 1 1 0 1

0 1 1 0 1 1

1 1 1 1 1 1