Serial I/O Communication: Understanding RS-232 and USB Protocols, Slides of Microcontrollers

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Serial I/O

Serial I/O

• A generic protocol used to communicate between computers.
  • Older than dirt – originally evolved from Morse Code
• The data is transmitted 1 bit at a time over a single wire
  • Often using a UART - "Universal Asynchronous Receiver/Transmitter”
• There is a protocol associated with the bus in order to convey

information – RS-

• When to start receiving (handshaking)
• Data packet format
• Speed
• MPC 555 “SCI” unit implements a subset of this.

Serial I/O

• The Receiver (Rx) and Transmitter (Tx) don't share any clock
  • this is why it is called "asynchronous”
• This is good because different computer systems can be connected
• This is bad because it limits the speed the bus can run due to non-

phase-locked time bases!

• Without a common clock, the Tx and Rx must agree on a common bus

speed (Baud rate)

• Use the START bit to “synchronize” the start of transactions

Serial I/O

• The Rx and Tx agree on a BAUD rate
• The Rx then "over samples" the incoming data by (at least) 16x

Serial I/O

• Serial Communications can be over a single wire
  • Uni-directional (called Simplex )
  • Bi-directional, not at the same time ( Half-Duplex )
• But most of the time its not:
  • Bi-directional at the same time ( Full-Duplex )

Protocol Options

• Baud Rate
  • RS-232 standard originally up to 19,200 bps
  • Most port UARTs fully support up to 115,200 bps
• Data size
  • 8 bits (full ASCII) or 7 bits (low ASCII)
• Parity
  • Used for error detection
  • Even parity – extra bit makes an even number of 1s
  • Odd parity – extra bit makes an odd number of 1s
• Stop Bits – 1 or 2
• Flow control – prevent overflows

NRZ

NRZI

• Non-return to zero (NRZ) - normal data transitions
  • The “Zero” refers to a dataless state in-between 1 and 0.
• NRZ Inverted (NRZI, not a good description, is not inverse of NRZ). A

transition for every zero bit.

• Strings of zeros means lots of transitions. Strings of „1‟s means steady line.

Bit Stuffing – a „0‟ is inserted after every six consecutive „1‟s in order to

ensure a signal transition so that receiver clock can remain synchronized

to the bit stream.

Bit stuffing done automatically by sending logic. Sync pattern starts data transmission and is seven „0‟s followed by a „1‟.

USB

• Unlike RS-232 (for which data can come in at any time),

USB is a polled bus.

• All transactions are initiated by the Host, which means that USB devices do not use interrupts (at least as we know them).

• Serial I/O on the MPC

QSMCM Module

• Includes 3 modules
  • QSPI (Queued Serial Peripheral Interface)
    • Motorola/Freescale custom serial-type interface
    • Synchronous and full-duplex
  • 2x SCI (Serial Communication Interface)
    • Implements subset of RS-232 serial interface
• Like the QADC, connects through the IMB3 bus interface

QSMCM Module

• Global Registers:
  • QSMCMMCR - QSMCM Configuration Register
    • The usual – IMB Freeze, Stop, and SUPV
  • QSMCM Interrupt Level Registers:
    • QDSCI_IL
    • QSPI_IL
    • These registers set the IMB3 Interrupt Level (0-31)
      • Encoded numerically – not with the USIU encodings
      • In USIU, 0-6 would show up as level 0 through 6, levels 7-31 as level 7

SCI Interface

• Setup steps:
  • Set the Baud Rate
  • Set the parity options
  • Data frame size (10 bits vs 11 bits)
  • Interrupt setup and enable
  • Transmit/Receive enable
• Optional: Make the transmission “Queued”

Setting the Baud Rate

SCCxR0 – SCI Control Reg 0

SCxBR controls Baud Rate (the others are reserved and should be 0)

fsys / (32 * SCxBR)

System clock for our board is 20 mhz