VHDL Synthesis Techniques: If-Then-Else, Case Statement, Wait Statement, and Control Loops, Slides of Computer Science

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Simple VHDL Synthesis Examples

If-then-else synthesis

if cond1 then Block_

elsif cond2 then Block_

elsif cond3 then Block

else Block_n

Block_

cond

Mux

Current o/ps

I/Ps

I/Ps

Block_

cond

Mux

I/Ps

I/Ps

Block_

cond

Mux

I/Ps

I/Ps

Block_n

Mux

I/Ps

Combinational Synthesis – Expensive, High Power but Fast

• A lower power variation also possible where I/Ps to blocks come via transparent latches that

are enabled by the same bits that are selects for the corresponding muxes

• This avoids signal transitions (that cause dynamic power consumption) in blocks that do not

need to be executed

Datapath when cond1=false

and cond2=true

Final o/p of

if-then-else

sequence

Daisy-chain

structure

I 0

I 1

I 0

I 1

I 0

I 1

I 0

I 1

Mux

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Case statement synthesis

case expression is

when choice1 => Block_

when choice2 => Block_

when others => Block_n

end case;

Combinational Synthesis – Expensive, High Power but Fast

• Faster than if-then-else synthesis if the larger

Case mux uses 2-level logic or the large Mux is

designed using D&C using 2:1 Muxes. In the

latter case, we get a (log n)- delay synthesis

versus n- delay in the case of if-then-else, where

n = # of choices in a case statement or if

conditions + 1 in an if-then-else statement

• Can also do a low power version where only

the selected block will process I/Ps via

transparent latches enabled by the choice-logic

o/ps (only one set of set of latches will be

enabled corresponding to the block to be

selected)

• Can also do a less expensive (and low

power) version which is partially sequential and

controlled by an FSM as in the if-then-else

statement

Mux

Block_ I/Ps

Block_ I/Ps

Block_n I/Ps

Final o/p of

case statement

choice

I/Ps(expressionvalue)

choice2 others

Encoder (n: log n)

select signal

Datapath when

choice 2 is activated

Mutually exclusive

Wait Statement Synthesis Issues

wait until (X=‘1’);

Next action;

Note: Design Compiler does not

Synthesize this wait statement

x != 1

x=

Next action

wait until (X’event and X=‘1’);

Next action;

1 Dx

Qx

X

Qx != 1

Qx =

ResetX = Next action

possible synthesis

poss. synth.

Reset (^) X

Control Loops

• for loops, while loops, etc. can be

synthesized as “looping FSMs”

controlling a datapath

• Example:

R2 := 0; R1 := X; AC = 1;

While (AC < 100000) loop

R2 := R2 + R1;

AC := AC*R2;

End loop;

• Synthesizing a for loop w/ n

iterations: Initialize counter & then

check its value after counting up

every “iteration” of the FSM’s loop

(or count down from an initial value

of n and check for 0)

R

R

∗

AC

Comparator

LT

ld_r

ld_r

ld_ac

Initialize State (AC, R1, R2, etc.)

Test State

ld_r2 = 1 (^) [R2 <- R2+R1]

LT = 1

ld_ac = 1 [AC <- AC*R2]

LT = 0

State after while loop

LT = 1  AC < 10 5

LT = 0  AC > 10 5

FSM for while loop; assumes 1 cc for each FU operation:

Datapath for statements In while loop: